Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor38
t
14
Write Burst ACK assertion after CS[x]
assertion
(2.5 + WS) × t
LPCck
– t
OD
(2.5 + WS) × t
LPCck
+ t
OD
ns A7.15
t
15
Write Burst DATA valid t
LPCck
– t
OD
— ns A7.16
t
16
Non-MUXed Mode: asynchronous write
Burst ADDR valid before write DATA
valid
0.5 × t
LPCck
– t
OD
0.5 × t
LPCck
+ t
OD
ns A7.17
t
17
MUXed Mode: ADDR cycle AL × 2 × t
LPCck
– t
OD
AL × 2 × t
LPCck
ns A7.18
t
18
MUXed Mode: ALE cycle AL × t
LPCck
AL × t
LPCck
ns A7.19
t
19
Non-MUXed Mode Page Burst: ADDR
cycle
t
LPCck
– t
OD
t
LPCck
ns A7.20
t
20
Non-MUXed Mode Page Burst: Burst
DATA (rd) input setup before next ADDR
cycle
t
OD
+ t
6
—
ns A7.21
t
21
Non-MUXed Mode Page Burst: Burst
DATA (rd) input hold after next ADDR
cycle
0
—
ns A7.22
t
22
MUXed Mode: non-Burst CS[x] pulse
width
(ALT × (AL × 2) + 2 + WS)
× t
LPCck
(ALT × (AL × 2) + 2 + WS)
× t
LPCck
ns A7.23
t
23
MUXed Mode: read Burst CS[x] pulse
width
[ALT (AL × 2) + 2 + WS
+
BBT/DS] × t
LPCck
[ALT × (AL × 2)+2+WS
+BBT/DS]
× t
LPCck
ns A7.24
t
24
MUXed Mode: write Burst CS[x] pulse
width
[ALT × (AL × 2) + 2.5 + WS
+ BBT/DS] × t
LPCck
[ALT × (AL × 2)+2.5+WS
+BBT/DS] × t
LPCck
ns A7.25
Table 23. LPC Timing (continued)
Sym Description Min Max Units SpecID