Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor46
Figure 25. Read Data Latch Timing in Symmetric Mode
Table 24. NFC Timing Characteristics in asymmetric mode(SYM=0)
1
1
T is the flash clock cycle.
T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)
T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)
Timing
parameter
Description Min. value Max. value Unit SpecID
t
CLS
NFC_CLE setup Time T + 1 — ns A8.1
t
CLH
NFC_CLE Hold Time T – 1 — ns A8.2
t
CS
NFC_CE[1:0] Setup Time 2T – 1 — ns A8.3
t
CH
NFC_CE[1:0] Hold Time 3T — ns A8.4
t
WP
NFC_WP Pulse Width T – 1 — ns A8.5
t
ALS
NFC_ALE Setup Time T – 1 — ns A8.6
t
ALH
NFC_ALE Hold Time T – 1 — ns A8.7
t
DS
Data Setup Time T – 2 — ns A8.8
t
DH
Data Hold Time T – 1 — ns A8.9
t
WC
Write Cycle Time 2T — ns A8.10
t
WH
NFC_WE Hold Time T – 1 — ns A8.11
t
RR
Ready to NFC_RE Low 5T + 2 — ns A8.12
t
RP
NFC_RE Pulse Width 1.5T – 1 — ns A8.13
t
RC
READ Cycle Time 2T — ns A8.14
t
REH
NFC_RE High Hold Time 0.5T — ns A8.15
tss
NFC_RE
NFIO[15:0]
NFC SYMMETRIC MODE(SYM=1)