Datasheet
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 47
3.3.9 PATA
The MPC5121e/MPC5123 ATA Controller (PATA) is completely software programmable. It can be programmed to operate
with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is
completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units
(
nanoseconds ).
ATA data setup and hold times, with respect to Read / Write strobes, are software programmable inside the ATA Controller. Data
setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the
ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and
ATA drive for different ATA protocols and their respective timing. See the MPC5121e Microcontroller Reference Manual.
The MPC5121e/MPC5123 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE
strobe in PIO and Multiword DMA modes.
• Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that
required by the ATA-4 specification.
• Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that
required by the ATA-4 specification.
Table 25. NFC Timing Characteristics in Symmetric mode(SYM=1)
1
1
T is the flash clock cycle.
T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)
T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)
Timing
Parameter
Description Min. value Max. value Unit SpecID
t
CLS
NFC_CLE Setup time T — ns A8.21
t
CLH
NFC_CLE Hold time T — ns A8.22
t
CS
NFC_CE[1:0] Setup time T- 2 — ns A8.23
t
CH
NFC_CE[1:0] Hold time 1.5T-1 — ns A8.24
t
WP
NFC_WE Pulse width 0.5T+1 — ns A8.25
t
ALS
NFC_ALE Setup time T — ns A8.26
t
ALH
NFC_ALE Hold time T — ns A8.27
t
DS
Data Setup time 0.5T-3 — ns A8.28
t
DH
Data Hold time 0.5T — ns A8.29
t
WC
Write Cycle time T — ns A8.30
t
WH
NFC_WE Hold time 0.5T-1 — ns A8.31
t
RR
Ready to NFC_RE low 5T+2 — ns A8.32
t
RP
NFC_RE pulse width 0.5T — ns A8.33
t
RC
Read Cycle time T — ns A8.34
t
REH
NFC_RE High hold time 0.5T — ns A8.35
t
SS
NFC Read Data setup time 9.6 — ns A8.36