Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor48
All ATA transfers are programmed in terms of system clock cycles ( IP bus clocks ) in the ATA Host Controller timing registers.
This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate
with the drive.
Faster ATA modes ( i.e., UDMA 0, 1, 2 ) are supported when the system is running at a sufficient frequency to provide adequate
data transfer rates. Adequate data transfer rates are a function of the following:
• The MPC5121e/MPC5123 operating frequency ( IP bus clock frequency )
• Internal MPC5121e/MPC5123 bus latencies
• Other system load dependent variables
The ATA clock is the same frequency as the IP bus clock in MPC5121e/MPC5123. See the MPC5121e Microcontroller
Reference Manual.
NOTE
All output timing numbers are specified for nominal 50 pF loads.
3.3.9.1 PATA Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface
in silicon, the bus transceiver used, the cable delay and cable skew. The parameters shown in
Table 3-26 specify the ATA timing.
Table 3-26. PATA Timing Parameters
Name Meaning Controlled by Value SpecID
T PATA Bus clock period MPC5121E/MPC5123 15 ns A9.1
t
i_ds
Set-up time ATA_DATA to ATA_IORDY edge (UDMA-in only) MPC5121E/MPC5123 2 ns A9.2
t
i_dh
Hold time ATA_IORDY edge to ATA_DATA (UDMA-in only) MPC5121E/MPC5123 5 ns A9.3
t
co
Propagation delay bus clock L-to-H to: ATA_CS0, ATA_CS1, ATA_DA2,
ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA,
ATA_BUFFER_EN
MPC5121E/MPC5123 2 ns A9.4
t
su
Set-up time ATA_DATA to bus clock L-to-H MPC5121E/MPC5123 2 ns A9.5
t
sui
Set-up time ATA_IORDY to bus clock H-to-L MPC5121E/MPC5123 2 ns A9.6
t
hi
Hold time ATA_IORDY to bus clock H to L MPC5121E/MPC5123 2 ns A9.7
t
skew1
Max difference in propagation delay bus clock L-to-H to any of following
signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0,
ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE),
ATA_BUFFER_EN
MPC5121E/MPC5123 1.7 ns A9.8
t
skew2
Max difference in buffer propagation delay for any of following signals:
ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR,
ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN
Transceiver A9.9
t
skew3
Max difference in buffer propagation delay for any of following signals:
ATA_IORDY, ATA_DATA (read)
Transceiver A9.10
t
buf
Max buffer propagation delay Transceiver A9.11
t
cable1
Cable propagation delay for ata_data Cable A9.12
t
cable2
Cable propagation delay for control signals: ATA_DIOR, ATA_DIOW,
ATA_IORDY, ATA_DMACK
Cable A9.13