Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 59
3.3.10 SATA PHY
1.5 Gbps SATA PHY Layer
See “Serial ATA: High Speed Serialized AT Attachment” Revision 1.0a, 7-January-2003.
3.3.11 FEC
AC Test Timing Conditions:
• Output Loading
All Outputs: 25 pF
Figure 36. Ethernet Timing Diagram – MII Rx Signal
t
li
t
li2
t
li2
> 0 — A9.74
t
li
t
li3
t
li3
> 0 — A9.75
t
cvh
t
cvh
t
cvh
= (time_cvh × T) – (t
skew1
+ t
skew2
) calculate and program
time_cvh .
1
A9.76
—
t
on
t
off
t
on
= time_on × T – t
skew1
t
off
= time_off × T – t
skew1
— A9.77
1
See the MPC5121e Microcontroller Reference Manual.
Table 32. MII Rx Signal Timing
Symbol Description Min Max Unit SpecID
1 RXD [ 3 : 0 ], RX_DV, RX_ER to RX_CLK setup 5 — ns A11.1
2 RX_CLK to RXD [ 3 : 0 ], RX_DV, RX_ER hold 5 — ns A11.2
3 RX_CLK pulse width high 35% 65% RX_CLK Period
1
1
RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification.
A11.3
4 RX_CLK pulse width low 35% 65% RX_CLK Period
1
A11.4
Table 31. Timing Parameters UDMA Out Burst (continued)
ATA
Parameter
UDMA Out
Timing
Parameter
Value How to meet SpecID
RX_CLK (Input)
RXD[3:0] (inputs)
RX_DV
RX_ER
1 2
3
4