Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor60
Figure 37. Ethernet Timing Diagram – MII Tx Signal
Figure 38. Ethernet Timing Diagram – MII Async
Table 33. MII Tx Signal Timing
Symbol Description Min Max Unit SpecID
5 TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER
invalid
3 — ns A11.5
6 TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER valid — 25 ns A11.6
7 TX_CLK pulse width high 35% 65% TX_CLK Period
1
1
The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide
a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See
the IEEE 802.3 Specification.
A11.7
8 TX_CLK pulse width low 35% 65% TX_CLK Period
1
A11.8
Table 34. MII Async Signal Timing
Symbol Description Min Max Unit SpecID
9 CRS, COL minimum pulse width 1.5 — TX_CLK Period A11.9
Table 35. MII Serial Management Channel Signal Timing
Symbol Description Min Max Unit SpecID
10 MDC falling edge to MDIO output delay 0 25 ns A11.10
11 MDIO ( input ) to MDC rising edge setup 10 — ns A11.11
12 MDIO ( input ) to MDC rising edge hold 0 — ns A11.12
13 MDC pulse width high
1
1
MDC is generated by MPC5121e/MPC5123 with a duty cycle of 50% except when MII_SPEED in the FEC
MII_SPEED control register is changed during operation. See the MPC5121e/MPC5123 Reference Manual.
160 — ns A11.13
14 MDC pulse width low
1
160 — ns A11.14
15 MDC period
2
400 — ns A11.15
TX_CLK (Input)
TXD[3:0] (Outputs)
TX_EN
TX_ER
5
6
7
8
CRS, COL
9