Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 65
Figure 43. TFT LCD Interface Timing Diagram – Horizontal Sync Pulse
Figure 44 shows the vertical timing (timing of one frame), including the vertical sync pulse and the data. All parameters shown
in the diagram are programmable.
Figure 44. TFT LCD Interface Timing Diagram – Vertical Sync Pulse
Table 38 shows timing parameters of signals.
Table 38. LCD Interface Timing Parameters – Pixel Level
Name Description Value Unit SpecID
t
PCP
Display Pixel Clock Period 15
1
ns A15.1
t
PWH
HSYNC Pulse Width PW_H × t
PCP
ns A15.2
t
BPH
HSYNC Back Porch Width BP_H × t
PCP
ns A15.3
1
2
3
DELTA_X
t
PWH
t
BPH
t
SW
t
FPH
DIU_CLK
DIU_LD[23:0]
DIU_HSYNC
DIU_DE
t
PCP
1
Invalid Data
Invalid Data
Start of line
t
HSP
1
2
3
DELTA_Y
t
PWV
t
BPV
t
SH
t
FPV
DIU_HSYNC
DIU_LD[23:0]
DIU_VSYNC
DIU_DE
t
HSP
1
(Line Data)
Start of Frame
Invalid Data
Invalid Data
t
VSP