Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor66
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H
parameters are programmed via the HSYN_PARA register; And the PW_V, BP_V and FP_V parameters are programmed via
the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions on these parameters.
Figure 45 shows the synchronous display interface timing for access level, and Table 39 lists the timing parameters.
Figure 45. LCD Interface Timing Diagram – Access Level
t
FPH
HSYNC Front Porch Width FP_H × t
PCP
ns A15.4
t
SW
Screen Width DELTA_X × t
PCP
ns A15.5
t
HSP
HSYNC (Line) Period (PW_H + BP_H + DELTA_X + FP_H) × t
PCP
ns A15.6
t
PWV
VSYNC Pulse Width PW_V × t
HSP
ns A15.7
t
BPV
VSYNC Back Porch Width BP_V × t
HSP
ns A15.8
t
FPV
VSYNC Front Porch Width FP_V × t
HSP
ns A15.9
t
SH
Screen Height DELTA_Y × t
HSP
ns A15.10
t
VSP
VSYNC (Frame) Period (PW_V + BP_V + DELTA_Y + FP_H) × t
HSP
ns A15.11
1
Display interface pixel clock period immediate value (in nanosecond).
Table 39. LCD Interface Timing Parameters – Access Level
Parameter Description Min Typ Max Unit SpecID
t
CKH
LCD Interface Pixel Clock High Time t
PCP
× 0.4 t
PCP
× 0.5 t
PCP
× 0.6 ns A15.12
t
CKL
LCD Interface Pixel Clock Low Time t
PCP
× 0.4 t
PCP
× 0.5 t
PCP
× 0.6 ns A15.13
t
DSU
LCD Interface Data Setup Time 5.0 — — ns A15.14
t
DHD
LCD Interface Data Hold Time 6.0 — — ns A15.15
t
CSU
LCD Interface Control Signal Setup Time 5.0 — — ns A15.16
t
CHD
LCD Interface Control Signal Hold Time 6.0 — — ns A15.17
Table 38. LCD Interface Timing Parameters – Pixel Level (continued)
Name Description Value Unit SpecID
t
CKH
t
CKL
t
DHD
t
DSU
t
CSU
DIU_HSYNC
DIU_VSYNC
DIU_DE
DIU_CLK
DIU_LD[23:0]
t
CHD