Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 67
3.3.16 SPDIF
The Sony/Philips Digital Interface (SPDIF) timing is totally asynchronous, therefore there is no need for relationship with the
clock.
3.3.17 CAN
The CAN functions are available as TX and CAN3/4_RX pins at normal IO pads and as CAN1/2 RX pins at the VBAT_RTC
domain. There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
3.3.18 I
2
C
This section specifies the timing parameters of the Inter-Integrated Circuit (I
2
C) interface. Refer to the I
2
C Bus Specification.
Table 40. I
2
C Input Timing Specifications – SCL and SDA
Symbol Description Min Max Units SpecID
1 Start condition hold time 2 — IP-Bus Cycle
1
1
Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual.
A18.1
2 Clock low time 8 — IP-Bus Cycle
1
A18.2
4 Data hold time 0.0 — ns A18.3
6 Clock high time 4 — IP-Bus Cycle
1
A18.4
7 Data setup time 0.0 — ns A18.5
8 Start condition setup time ( for repeated start condition only ) 2 — IP-Bus Cycle
1
A18.6
9 Stop condition setup time 2 — IP-Bus Cycle
1
A18.7
Table 41. I
2
C Output Timing Specifications – SCL and SDA
Symbol Description Min Max Units SpecID
1
1
1
Programming IFDR with the maximum frequency results in the minimum output timings listed. The I
2
C interface is designed to
scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and
division values programmed in IFDR.
Start condition hold time 6 — IP-Bus Cycle
2
2
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA
takes to reach a high level depends on external signal capacitance and pull-up resistor values.
A18.8
2
1
Clock low time 10 — IP-Bus Cycle
2
A18.9
3
3
3
Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual.
SCL / SDA rise time — 7.9 ns A18.10
4
1
Data hold time 7 — IP-Bus Cycle
2
A18.11
5
1
SCL / SDA fall time — 7.9 ns A18.12
6
1
Clock high time 10 — IP-Bus Cycle
2
A18.13
7
1
Data setup time 2 — IP-Bus Cycle
2
A18.14
8
1
Start condition setup time ( for repeated start condition only ) 20 — IP-Bus Cycle
2
A18.15
9
1
Stop condition setup time 10 — IP-Bus Cycle
2
A18.16