Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 69
Figure 47. Timing Diagram – 8, 16, 24, and 32-bit CODEC/I
2
S Master Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Table 43. Timing Specifications – 8, 16, 24, and 32-bit CODEC/I
2
S Slave Mode
Symbol Description Min Typ Max Units SpecID
1 Bit Clock cycle time 40.0 — — ns A20.9
2 Clock duty cycle — 50 — %
1
1
Bit Clock cycle time
A20.10
3 FrameSync setup time 1.0 — — ns A20.11
4 Output Data valid after clock edge — — 14.0 ns A20.12
5 Input Data setup time 1.0 — — ns A20.13
6 Input Data hold time 1.0 — — ns A20.14
BitClk Output
5
3
4
3
4
(CLKPOL=0)
BitClk Output
(CLKPOL=1)
FrameSync Output
(SyncPol = 1)
TxD
Output
6
7
8
FrameSync Output
(SyncPol = 0)
RxD
Input
1
2
2