Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 71
Figure 49. Timing Diagram – AC97 Mode
3.3.20.3 SPI Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Table 45. Timing Specifications – SPI Master Mode, Format 0 (CPHA = 0)
Symbol Description Min Max Units SpecID
1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.26
2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.27
3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A20.28
4 Output Data valid after Slave Select (SS) — 8.9 ns A20.29
5 Output Data valid after SCK — 8.9 ns A20.30
6 Input Data setup time 6.0 — ns A20.31
7 Input Data hold time 1.0 — ns A20.32
8 Slave disable lag time — TSCK ns A20.33
9 Sequential Transfer delay, programmable in the PSC CTUR / CTLR register 15.0 — ns A20.34
10 Clock falling time — 7.9 ns A20.35
11 Clock rising time — 7.9 ns A20.36
BitClk
(CLKPOL=0)
FrameSync
(SyncPol = 1)
Sdata_out
Output
Input
6
Output
Sdata_in
Input
1
4
3
5
2
7