Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 73
Figure 51. Timing Diagram – SPI Slave Mode, Format 0 (CPHA = 0)
NOTE
Output timing is specified at a nominal 50 pF load.
Table 47. Timing Specifications – SPI Master Mode, Format 1 (CPHA = 1)
Symbol Description Min Max Units SpecID
1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.46
2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.47
3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A20.48
4 Output data valid — 8.9 ns A20.49
5 Input Data setup time 6.0 — ns A20.50
6 Input Data hold time 1.0 — ns A20.51
7 Slave disable lag time — TSCK ns A20.52
8 Sequential Transfer delay, programable in the PSC CTUR / CTLR register 15.0 — ns A20.53
9 Clock falling time — 7.9 ns A20.54
10 Clock rising time — 7.9 ns A20.55
SCK
(CLKPOL=0)
SCK
(CLKPOL=1)
MOSI
Input
Input
Input
SS
Input
MISO
Output
1
2
2
9
3
7
4
6
5
8