Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor76
3.3.23 IEEE 1149.1 (JTAG)
Figure 54. Timing Diagram – JTAG Clock Input
Table 51. JTAG Timing Specification
Symbol Characteristic Min Max Unit SpecID
— TCK frequency of operation 0 25 MHz A23.1
1 TCK cycle time 40 — ns A23.2
2 TCK clock pulse width measured at 1.5 V 1.08 — ns A23.3
3 TCK rise and fall times 0 3 ns A23.4
4 TRST setup time to tck falling edge
1
1
TRST is an asynchronous signal. The setup time is for test purposes only.
10 — ns A23.5
5 TRST assert time 5 — ns A23.6
6 Input data setup time
2
2
Non-test, other than TDI and TMS, signal input timing with respect to TCK.
5 — ns A23.7
7 Input data hold time

15 — ns A23.8
8 TCK to output data valid
3
3
Non-test, other than TDO, signal output timing with respect to TCK.
0 30 ns A23.9
9 TCK to output high impedance
3
0 30 ns A23.10
10 TMS, TDI data setup time. 5 — ns A23.11
11 TMS, TDI data hold time. 1 — ns A23.12
12 TCK to TDO data valid. 0 15 ns A23.13
13 TCK to TDO high impedance. 0 15 ns A23.14
TCK
VMVM VM
3
3
2
2
1
VM = Midpoint Voltage