Datasheet

System Design Information
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 79
4 System Design Information
4.1 Power Up/Down Sequencing
Power sequencing between the 1.4 V power supply V
DD_CORE
and the remaining supplies is required to prevent excessive
current during power up phase.
The required power sequence is as follows:
•Use 12 V/millisecond or slower time for all supplies.
• Power up V
DD_IO
, PLL_AV
DD
, V
BAT_RTC
(if not applied permanently), V
DD_MEM_IO
, USB PHY, and SATA PHY
supplies first in any order and then power up V
DD_CORE
. If required, AV
DD_FUSEWR
should be powered up afterwards.
• All the supplies must reach the specified operating conditions before the PORESET can be released.
• For power down, drop AV
DD_FUSEWR
to 0 V first, drop V
DD_CORE
to 0 V, and then drop all other supplies.
•V
DD_CORE
should not exceed V
DD_IO
, V
DD_MEM_IO
, V
BAT_RTC
, or PLL_AV
DD
s by more than 0.4 V at any time,
including power-up.
4.2 System and CPU Core AVDD Power Supply Filtering
Each of the independent PLL power supplies require filtering external to the device. The following drawing Figure 59 is a
recommendation for the required filter circuit.
Each circuit should be placed as close as possible to the specific AV
DD
pin being supplied to minimize noise coupled from
nearby circuits.
All traces should be as low impedance as possible, especially ground pins to the ground plane.
The filter for System/Core PLLV
DD
to V
SS
should be connected to the power and ground planes, respectively, not fingers of the
planes.
In addition to keeping the filter components for System/Core PLLV
DD
as close as practical to the body of the MPC5121e as
previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise
onto the portion of that supply between the filter and the MPC5121e.
Figure 59. Power Supply Filtering
The capacitors for C2 in Figure 59 should be rated X5R or better due to temperature performance. It is recommended to add a
bypass capacitance of at least 1 µF for the V
BAT_RTC
pin.
4.3 Connection Recommendations
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to
V
DD_IO
. Unused active high inputs should be connected to V
SS
. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD
and V
SS
pins of the MPC5121e/MPC5123.
The unused AV
DD_FUSEWR
power should be connected to V
SS
directly or via a resistor.
For DDR or LPDDR modes the unused pins MVTT[3:0] for DDR2 Termination voltage can be unconnected.
AVDD device pin
Power supply
source
R1 = 10 
C1 = 1 F C2 = 0.1 F