Datasheet

System Design Information
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 81
4.4.2 Pull-Up Requirements for the PCI Control Lines
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain
stable values when no agent is actively driving the bus. This includes
PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,
PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
Refer to the PCI Local Bus specification.
4.5 JTAG
The MPC5121e/MPC5123 provides you with an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides
a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port.
The COP Interface provides access to the MPC5121e/MPC5123’s embedded e300 processor and to other on-chip resources.
This interface provides a means for executing test routines and for performing software development and debug functions.
4.5.1 TRST
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset
performance, the
TRST signal must be asserted during power-on reset.
4.5.1.1 TRST and PORESET
The JTAG interface can control the direction of the MPC5121e/MPC5123 I/O pads via the boundary scan chain. The JTAG
module must be reset before the MPC5121e/MPC5123 comes out of power-on reset; do this by asserting
TRST before
PORESET is released.
For more details refer to the Reset and JTAG Timing Specification.
Figure 62. PORESET vs. TRST
4.5.2 e300 COP / BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
4.5.2.1 Boards Interfacing the JTAG Port via a COP Connector
The MPC5121e/MPC5123 functional pin interface and internal logic provides access to the embedded e300 processor core
through the Freescale standard COP
/ BDM interface. Table 53 gives the COP / BDM interface signals. The pin order shown
reflects only the COP / BDM connector order.
TRST
PORESET
Required assertion of TRST Optional assertion of TRST