Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 41
Figure 31. Timing Diagram—USB Output Line
1.3.12 SPI
NOTE
Output timing is specified at a nominal 50 pF load.
Table 36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
Sym Description Min Max Units SpecID
1 Cycle time 4 1024 IP-Bus Cycle
(1)
1
Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
A11.1
2 Clock high or low time 2 512 IP-Bus Cycle
(1)
A11.2
3 Slave select to clock delay 15.0 — ns A11.3
4 Output Data valid after Slave Select (SS
) — 20.0 ns A11.4
5 Output Data valid after SCK — 20.0 ns A11.5
6 Input Data setup time 20.0 — ns A11.6
7 Input Data hold time 20.0 — ns A11.7
8 Slave disable lag time 15.0 — ns A11.8
9 Sequential transfer delay 1 — IP-Bus Cycle
(1)
A11.9
10 Clock falling time — 7.9 ns A11.10
11 Clock rising time — 7.9 ns A11.11
11
2
4
3
3
4
USB_OE
USB_TXN
USB_TXP