Datasheet

2 MPC555 Product Brief

Block Diagram

• Extensive system development support

— On-chip watchpoints and breakpoints

— Program flow tracking

— BDM on-chip emulation development interface

1.1 Block Diagram

Figure 1 is a block diagram of the MPC555.

Figure 1. MPC555 Block Diagram

1.2 Key Features

The MPC555 key features are explained in the following sections.

1.2.1 Four-Bank Memory Controller

• Works with SRAM, EPROM, Flash EEPROM, and other peripherals

• Byte write enables

• 32-bit address decodes with bit masks

USIU

RCPU

Burst

Interface

256 Kbytes

Flash

192 Kbytes

Flash

16 Kbytes

SRAM

10 Kbytes

SRAM

L2U

E-bus

UIMB

QADC QADC QSMCM

TouCAN

TPU3

DPTRAM

TPU3 TouCAN MIOS1

L-bus

IMB3

U-bus

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com