Document Number: MPC5566 Rev. 3, September 2012 Freescale Data Sheet: Technical Data MPC5566 Microcontroller Data Sheet This document provides electrical specifications, pin assignments, and package diagrams for the MPC5566 microcontroller device. For functional characteristics, refer to the MPC5566 Microcontroller Reference Manual. 1 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . .
Overview The MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565x. The host processor core of the MPC5566 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to significantly reduce the code size footprint. The MPC5566 has two levels of memory hierarchy.
Ordering Information 2 Ordering Information M PC 5566 M ZP 80 R Qualification status Core code Device number Temperature range Package identifier Operating frequency (MHz) Tape and reel status Temperature Range M = –40° C to 125° C Package Identifier ZP = 416PBGA SnPb VR = 416PBGA Pb-free Operating Frequency 80 = 80 MHz 112 = 112 MHz 132 = 132 MHz 144 = 144 MHz Note: Not all options are available on all devices. Refer to Table 1.
Electrical Characteristics 3 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU. 3.1 Maximum Ratings Table 2. Absolute Maximum Ratings 1 Spec Characteristic Symbol Min. Max. Unit 1 1.5 V core supply voltage 2 VDD –0.3 1.7 V 2 Flash program/erase voltage VPP –0.3 6.5 V 4 Flash read voltage VFLASH –0.3 4.6 V 5 SRAM standby voltage VSTBY –0.3 1.
Electrical Characteristics Table 2. Absolute Maximum Ratings 1 (continued) Spec 28 29 Characteristic Symbol Min. Max. Maximum solder temperature 11 Lead free (Pb-free) Leaded (SnPb) TSDR — — 260.0 245.0 Moisture sensitivity level 12 MSL — 3 Unit o C 1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed.
Electrical Characteristics 3.2.1 General Notes for Specifications at Maximum Junction Temperature An estimation of the device junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA PD) where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons.
Electrical Characteristics At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RJB = junction-to-board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable.
Electrical Characteristics The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction.
Electrical Characteristics 3.5 ESD (Electromagnetic Static Discharge) Characteristics Table 5.
Electrical Characteristics Table 6. VRC and POR Electrical Specifications (continued) Spec 9 Characteristic Absolute value of slew rate on power supply pins Symbol Min. Max. Units — — 50 V/ms 60 — — 65 — — 85 500 — o 10 Required gain at Tj: – 40 C IDD IVRCCTL (@ fsys = fMAX) 6, 7, 8, 9 25o C 150o C BETA 10 1 The internal POR signals are VPOR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates.
Electrical Characteristics 1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR negates again. All oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, no delta between VRC33 and VDDSYN is required for the VRC to operate within specification.
Electrical Characteristics During initial power ramp-up, when Vstby is 0.6v or above. a typical current of 1-3mA and maximum of 4mA may be seen until VDD is applied. This current will not reoccur until Vstby is lowered below Vstby min. specification. Figure 2 shows an approximate interpolation of the ISTBY worst-case specification to estimate values at different voltages and temperatures.
Electrical Characteristics 3.7.1 Input Value of Pins During POR Dependent on VDD33 When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates.
Electrical Characteristics 3.8 DC Electrical Specifications Table 9. DC Electrical Specifications (TA = TL to TH) Spec 1 Characteristic Core supply voltage (average DC RMS voltage) 1 Symbol Min Max. Unit VDD 1.35 1.65 V VDDE 1.62 3.6 V 2 Input/output supply voltage (fast input/output) 3 Input/output supply voltage (slow and medium input/output) VDDEH 3.0 5.25 V 4 3.3 V input/output buffer voltage VDD33 3.0 3.6 V 5 Voltage regulator control input voltage VRC33 3.0 3.
Electrical Characteristics Table 9. DC Electrical Specifications (TA = TL to TH) (continued) Spec Characteristic Symbol Min Max. Unit IDD IDD IDD IDD — — — — 650 530 820 650 mA mA mA mA IDD IDD — — 750 585 mA mA IDD IDD IDD IDD — — — — 630 500 785 630 mA mA mA mA IDD IDD — — 710 550 mA mA IDD IDD IDD IDD — — — — 600 450 680 500 mA mA mA mA IDD IDD — — 650 490 mA mA IDD IDD IDD IDD — — — — 490 360 545 400 mA mA mA mA IDD IDD — — 530 395 mA mA 27d RAM standby current.
Electrical Characteristics Table 9. DC Electrical Specifications (TA = TL to TH) (continued) Spec 28 29 30 31 Characteristic Symbol Min Max. Unit VDD33 13 IDD_33 — 2 + (values derived from procedure of footnote 13) mA VFLASH IVFLASH — 10 mA VDDSYN IDDSYN — 15 mA Operating current 5.0 V supplies (12 MHz ADCLK): VDDA (VDDA0 + VDDA1) Analog reference supply current (VRH, VRL) VPP IDD_A IREF IPP — — — 20.0 1.0 25.
Electrical Characteristics Table 9. DC Electrical Specifications (TA = TL to TH) (continued) Spec Characteristic Symbol Min Max. Unit 41 VSSSYN to VSS differential voltage VSSSYN – VSS –50 50 mV 42 VRCVSS to VSS differential voltage VRCVSS – VSS –50 50 mV 43 VDDF to VDD differential voltage VDDF – VDD –100 100 mV 43a VRC33 to VDDSYN differential voltage VRC33 – VDDSYN –0.1 0.1 19 V VIDIFF –2.5 2.
Electrical Characteristics 3.8.1 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. Table 10.
Electrical Characteristics 3.8.2 I/O Pad VDD33 Current Specifications The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins.
Electrical Characteristics 3.9 Oscillator and FMPLL Electrical Characteristics Table 12. FMPLL Electrical Specifications (VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.
Electrical Characteristics Table 12. FMPLL Electrical Specifications (continued) (VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.
Electrical Characteristics 3.10 eQADC Electrical Characteristics Table 13. eQADC Conversion Specifications (TA = TL to TH) Spec Characteristic Symbol Minimum Maximum Unit FADCLK 1 12 MHz 13 + 2 (15) 14 + 2 (16) 13 + 128 (141) 14 + 128 (142) 1 ADC clock (ADCLK) frequency 1 Conversion cycles Differential Single ended CC 2 3 Stop mode recovery time 2 TSR 10 — s — 1.
Electrical Characteristics 3.11 H7Fa Flash Memory Electrical Characteristics Table 14. Flash Program and Erase Specifications (TA = TL to TH) Spec 3 1 2 3 4 5 6 Flash Program Characteristic Doubleword (64 bits) program time 4 Symbol Min. Typical 1 Initial Max. 2 Max.
Electrical Characteristics Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. Table 16. FLASH_BIU Settings vs.
Electrical Characteristics Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V) 1 (continued) Spec SRC / DSC (binary) Pad Out Delay 2, 3, 4 (ns) Rise / Fall 4, 5 (ns) Load Drive (pF) 16 8 50 43 30 200 34 15 50 61 35 200 192 100 50 239 125 200 2.7 10 2.5 20 2.4 30 2.3 50 11 2 Medium high voltage (MH) 01 00 00 3 01 Fast 3.1 10 11 1 2 3 4 5 4 Pullup/down (3.6 V max) — — 7500 50 5 Pullup/down (5.
Electrical Characteristics Table 18. Derated Pad AC Specifications (VDDEH = 3.3 V, VDDE = 3.3 V) 1 (continued) Spec SRC/DSC (binary) Pad Out Delay 2, 3, 4 (ns) Rise / Fall 3, 5 (ns) Load Drive (pF) 2.4 10 2.2 20 2.1 30 2.1 50 00 3 01 Fast 3.2 10 11 1 2 3 4 5 4 Pullup/down (3.6 V max) — — 7500 50 5 Pullup/down (5.5 V max) — — 9500 50 These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at: VDD = 1.35–1.
Electrical Characteristics Table 19. Reset and Configuration Pin Timing 1 (continued) Spec 1 Characteristic Symbol Min. Max. Unit 3 PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid tRCSU 10 — tCYC 4 PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid tRCH 0 — tCYC Reset timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH. 2 RESET 1 RSTOUT 3 PLLCFG BOOTCFG RSTCFG WKPCFG 4 Figure 5. Reset and Configuration Pin Timing 3.13.2 IEEE 1149.
Electrical Characteristics Table 20. JTAG Pin AC Electrical Characteristics 1 (continued) Spec 1 Characteristic Symbol Min. Max. Unit 12 TCK falling-edge to output valid out of high impedance tBSDVZ — 50 ns 13 TCK falling-edge to output high impedance (Hi-Z) tBSDHZ — 50 ns 14 Boundary scan input valid to TCK rising-edge tBSDST 50 — ns 15 TCK rising-edge to boundary scan input invalid tBSDHT 50 — ns These specifications apply to JTAG boundary scan only.
Electrical Characteristics TCK 4 5 TMS, TDI 6 8 7 TDO Figure 7. JTAG Test Access Port Timing TCK 10 JCOMP 9 Figure 8. JTAG JCOMP Timing MPC5566 Microcontroller Data Sheet, Rev.
Electrical Characteristics TCK 11 13 Output signals 12 Output signals 14 15 Input signals Figure 9. JTAG Boundary Scan Timing MPC5566 Microcontroller Data Sheet, Rev.
Electrical Characteristics 3.13.3 Nexus Timing Table 21. Nexus Debug Port Timing 1 Spec Characteristic 1 MCKO cycle time 2 MCKO duty cycle 3 Min. Max. Unit tMCYC 12 8 tCYC tMDC 40 60 % tMDOV –1.5 3.0 ns MCKO low to MSEO data valid 3 tMSEOV –1.5 3.0 ns 5 MCKO low to EVTO data valid 3 tEVTOV –1.5 3.0 ns 6 EVTI pulse width tEVTIPW 4.
Electrical Characteristics TCK 10 11 TMS, TDI 12 TDO Figure 11. Nexus TDI, TMS, TDO Timing MPC5566 Microcontroller Data Sheet, Rev.
Electrical Characteristics 3.13.4 External Bus Interface (EBI) Timing Table 22 lists the timing information for the external bus interface (EBI). Table 22. Bus Operation Timing 1 Characteristic and Description Spec 1 CLKOUT period 2 CLKOUT duty cycle 3 4 CLKOUT rise time CLKOUT fall time CLKOUT positive edge to output signal invalid or Hi-Z (hold time) 5 External Bus Frequency 2, 3 Symbol 40 MHz 56 MHz 67 MHz Unit 72 MHz Min Max Min Max Min Max Min Max TC 25.0 — 17.9 — 15.
Electrical Characteristics Table 22. Bus Operation Timing 1 Spec Characteristic and Description CLKOUT positive edge to output signal valid (output delay) 6 Symbol 40 MHz Min tCOV Max 56 MHz Min 10.0 6 — Max 67 MHz Min 7.5 6 — 11.0 Max 72 MHz Min 6.0 6 — 8.5 Unit 5.0 6 EBTS = 0 ns — 6.0 7.
Electrical Characteristics Table 22. Bus Operation Timing 1 Characteristic and Description Spec External Bus Frequency 2, 3 Symbol 40 MHz 56 MHz 67 MHz 72 MHz Unit Min Max Min Max Min Max Min Max tCCIS 11.0 — 8.0 — 6.0 — 4.0 — ns tCIH 1.0 — 1.0 — 1.0 — 1.0 — ns tCCIH 1.0 — 1.0 — 1.0 — 1.
Electrical Characteristics Voh_f VDDE 2 CLKOUT Vol_f 2 3 2 4 1 Figure 12. CLKOUT Timing VDDE 2 CLKOUT 6 5 VDDE 2 5 Output bus VDDE 2 6 5 5 Output signal VDDE 2 6 Output signal VDDE 2 Figure 13. Synchronous Output Timing MPC5566 Microcontroller Data Sheet, Rev.
Electrical Characteristics CLKOUT VDDE 2 7 8 Input bus VDDE 2 7 8 Input signal VDDE 2 Figure 14. Synchronous Input Timing 3.13.5 External Interrupt Timing (IRQ Signals) Table 23. External Interrupt Timing 1 Spec 1 2 Characteristic Symbol Min. Max. Unit 1 IRQ pulse-width low tIPWL 3 — tCYC 2 IRQ pulse-width high TIPWH 3 — tCYC 3 IRQ edge-to-edge time 2 tICYC 6 — tCYC IRQ timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH.
Electrical Characteristics IRQ 2 1 3 Figure 15. External Interrupt Timing 3.13.6 eTPU Timing Table 24. eTPU Timing 1 Spec 1 2 1 2 Characteristic eTPU input channel pulse width eTPU output channel pulse width Symbol Min. Max Unit tICPW 4 — tCYC — tCYC tOCPW 2 2 eTPU timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH. This specification does not include the rise and fall times.
Electrical Characteristics 3.13.7 eMIOS Timing Table 25. eMIOS Timing 1 Spec 1 2 1 2 Characteristic Symbol Min. Max. Unit tMIPW 4 — tCYC — tCYC eMIOS input pulse width eMIOS output pulse width tMOPW 1 2 eMIOS timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH. This specification does not include the rise and fall times.
Electrical Characteristics Table 26.
Electrical Characteristics 2 3 PCSx 1 4 SCK output (CPOL=0) 4 SCK output (CPOL=1) 9 SIN 10 First data Last data Data 12 SOUT First data 11 Data Last data Figure 18. DSPI Classic SPI Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) 10 SCK output (CPOL=1) 9 SIN Data First data 12 SOUT First data Last data 11 Data Last data Figure 19. DSPI Classic SPI Timing—Master, CPHA = 1 MPC5566 Microcontroller Data Sheet, Rev.
Electrical Characteristics 3 2 SS 1 4 SCK input (CPOL=0) 4 SCK input (CPOL=1) 5 First data SOUT 9 6 Data Last data Data Last data 10 First data SIN 11 12 Figure 20. DSPI Classic SPI Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) 11 5 12 SOUT First data 9 SIN Data Last data Data Last data 6 10 First data Figure 21. DSPI Classic SPI Timing—Slave, CPHA = 1 MPC5566 Microcontroller Data Sheet, Rev.
Electrical Characteristics 3 PCSx 4 1 2 SCK output (CPOL=0) 4 SCK output (CPOL=1) 9 SIN 10 First data Last data Data 12 SOUT 11 First data Last data Data Figure 22. DSPI Modified Transfer Format Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) 10 9 SIN First data Data 12 SOUT First data Data Last data 11 Last data Figure 23. DSPI Modified Transfer Format Timing—Master, CPHA = 1 MPC5566 Microcontroller Data Sheet, Rev.
Electrical Characteristics 3 2 SS 1 SCK input (CPOL=0) 4 4 SCK input (CPOL=1) 12 11 5 First data SOUT Data Last data 10 9 Data First data SIN 6 Last data Figure 24. DSPI Modified Transfer Format Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) 11 5 6 12 First data SOUT 9 Last data Data Last data 10 First data SIN Data Figure 25. DSPI Modified Transfer Format Timing—Slave, CPHA = 1 7 8 PCSS PCSx Figure 26.
Electrical Characteristics 3.13.9 eQADC SSI Timing Table 27. EQADC SSI Timing Characteristics Spec Rating Symbol Minimum Typical Maximum Unit tFCK 2 — 17 tSYS_CLK 2 FCK period (tFCK = 1 fFCK) 1, 2 3 Clock (FCK) high time tFCKHT tSYS_CLK 6.5 — 9 (tSYS_CLK 6.5) ns 4 Clock (FCK) low time tFCKLT tSYS_CLK 6.5 — 8 (tSYS_CLK 6.5) ns 5 SDS lead / lag time tSDS_LL –7.5 — +7.5 ns 6 SDO lead / lag time tSDO_LL –7.5 — +7.
Electrical Characteristics 3.14 Fast Ethernet AC Timing Specifications Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic (TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC signals are independent of the system clock frequency (part speed designation). 3.14.
Electrical Characteristics 3.14.2 MII FEC Transmit Signal Timing FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, FEC_TX_CLK The transmitter functions correctly up to the FEC_TX_CLK maximum frequency of 25 MHz plus one percent. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_TX_CLK frequency.
Electrical Characteristics 3.14.3 MII FEC Asynchronous Inputs Signal Timing FEC_CRS and FEC_COL Table 30 lists MII FEC asynchronous input signal timing. Table 30. MII FEC Asynchronous Inputs Signal Timing Spec 9 Characteristic Min. Max Unit 1.5 — FEC_TX_CLK period FEC_CRS, FEC_COL minimum pulse width Figure 30 shows MII FEC asynchronous input timing listed in Table 30. FEC_CRS, FEC_COL 9 Figure 30. MII FEC Asynchronous Inputs Timing Diagram 3.14.
Electrical Characteristics 14 15 FEC_MDC (output) 10 FEC_MDIO (output) 11 FEC_MDIO (input) 12 13 Figure 31. MII FEC Serial Management Channel Timing Diagram MPC5566 Microcontroller Data Sheet, Rev.
Mechanicals 4 Mechanicals 4.1 MPC5566 416 PBGA Pinout Figure 32, Figure 33, and Figure 34 show the pinout for the MPC5566 416 PBGA package. The alternate Fast Ethernet Controller (FEC) signals are multiplexed with the data calibration bus signals. NOTE The MPC5500 devices are pin compatible for software portability and use the primary function names to label the pins in the BGA diagram.
Mechanicals 1 2 3 4 5 6 7 8 9 10 11 12 13 A VSS VSTBY AN37 AN11 VDDA1 AN16 AN1 AN5 VRH AN23 AN27 AN28 AN35 B VDD VSS AN36 AN39 AN19 AN20 AN0 AN4 REF BYPC AN22 AN26 AN31 AN32 VDD VSS AN8 AN17 VSSA1 AN21 AN3 AN7 VRL AN25 AN30 AN33 VDD VSS AN38 AN9 AN10 AN18 AN2 AN6 AN24 AN29 AN34 C VDD33 D ETPUA ETPUA 30 31 E ETPUA ETPUA VDDEH 28 29 1 F ETPUA ETPUA ETPUA VDDEH 24 27 26 1 G ETPUA ETPUA ETPUA ETPUA 23 22 25 21 H ETPUA ETPUA ETPUA ETPUA 20
Mechanicals 14 15 16 17 18 19 20 21 GPIO 205 22 23 24 25 26 VDD VDD33 VSS VSSA0 AN15 ETRIG ETPUB ETPUB ETPUB ETPUB 1 18 20 24 27 VSSA0 AN14 ETRIG ETPUB ETPUB ETPUB ETPUB MDO10 MDO7 0 21 25 28 31 MDO4 MDO0 VSS VDDA0 AN13 ETPUB ETPUB ETPUB ETPUB MDO9 19 22 26 30 MDO6 MDO1 VSS VDDE7 VDD C VDDEH AN12 9 ETPUB ETPUB ETPUB ETPUB MDO5 16 17 23 29 MDO2 VDDEH 8 VSS VDDE7 TCK TDI D VDDE7 TMS TDO TEST E MSEO0 JCOMP EVTI EVTO F MSEO1 MCKO GPIO 204 ETPUB G 15 MDO11 MD
Mechanicals 4.2 MPC5566 416-Pin Package Dimensions The package drawings of the MPC5566 416 pin TEPBGA package are shown in Figure 36. Figure 36. MPC5566 416 TEPBGA Package MPC5566 Microcontroller Data Sheet, Rev.
Mechanicals Figure 36. MPC5566 416 TEPBGA Package (continued) MPC5566 Microcontroller Data Sheet, Rev.
Revision History for the MPC5566 Data Sheet 5 Revision History for the MPC5566 Data Sheet The history of revisions made to this data sheet are listed and described in this section. The information that has changed from a previous revision of this document to the current revision is listed for each revision and are grouped in the following categories: • Global and text changes • Table and figure changes Within each category, the information that has changed is listed in sequential order. 5.
Revision History for the MPC5566 Data Sheet Table 33. Changes Between Rev. 1.0 and 2.0 Location Description of Changes Table 3, MPC5566 Thermal Characteristics: Changed for production purposes, footnote 1 from: Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
Revision History for the MPC5566 Data Sheet 5.3 Information Changed Between Revisions 0.0 and 1.0 The following table lists the global changes made throughout the document, as well as the changes to sections of text not contained in a figure or table. Table 34. Global and Text Changes Between Rev. 0.0 and 1.0 Location Description of Changes Global Changes • Third paragraph and throughout the document, replaced: • kilobytes with KB. • megabytes with MB.
Revision History for the MPC5566 Data Sheet Table 34. Global and Text Changes Between Rev. 0.0 and 1.0 (continued) Location Description of Changes Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33:” Added the following text directly before this section and after Table 8 Pin Status for Medium / Slow Pads During the Power-on Sequence: ‘The values in Table 7 and Table 8 do not include the effect of the weak pull devices on the output pins during power up.
Revision History for the MPC5566 Data Sheet Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued) Location Description of Changes Table 2, Absolute Maximum Ratings: • Deleted Spec 3, “Flash core voltage.” • Spec 12 “DC Input Voltage”: Deleted from second line‘. . .except for eTPUB15 and SINB (DSPI_B_SIN)’ leaving VDDEH powered I/O pads. Deleted third line ‘VDDEH powered by I/O pads (eTPUB15 and SINB), including the min. and max values of -0.3 and 6.
Revision History for the MPC5566 Data Sheet Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued) Location Description of Changes Table 5, ESD Characteristics: Added (Electromagnetic Static Discharge) in the table title. Table 6, VCR/POR Electrical Specifications: • Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5 negate (internal POR).
Revision History for the MPC5566 Data Sheet Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued) Location Description of Changes Table 9, DC Electrical Specifications: • Spelled out meaning of the slash ‘/’ as ‘and’ as well as ‘I/O’ as ‘input/output.’ Sentence still very confusing. Deleted ‘input/output’ from the specs to improve clarity. • Spec 20, column 2, Characteristics,’ Slow and medium output high voltage (IOH_S = –2.
Revision History for the MPC5566 Data Sheet Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued) Location Description of Changes Table 9, DC Electrical Specifications (continued) • Spec 27e, Operating current 1.5 V supplies @ 147 MHz: Added maximum values for 8-way cache: all with footnote 11. -- 1.65 typical = 650, -- 1.35 typical = 530, -- 1.65 high = 820, -- 1.35 high = 650. Added 4-way cache: all with footnote 11. -- 1.65 high = 720 -- 1.
Revision History for the MPC5566 Data Sheet Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued) Location Description of Changes Table 15, Flash EEPROM Module Life: • Replaced (Full Temperature Range) with (TA = TL – TH) in the table title. • Spec 1b, Min. column value changed from 10,000 to 1,000. Table 16, FLASH BIU Settings vs. Frequency of Operations: • ‘Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist.
Revision History for the MPC5566 Data Sheet Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued) Location Description of Changes Table 22, Bus Operation Timing: • Added a column to the table for 72 MHz minimum and maximum bus frequencies. • Spec 1: 72 MHz Min. column = 13.3. • Specs 5 and 6: CLKOUT positive edge to output signals invalid of high: Corrected format to show the bus timing values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
Revision History for the MPC5566 Data Sheet Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued) Location Description of Changes Table 27, EQADC SSI Timing Characteristics: • • • • Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’ Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’ Spec 1: FCK frequency -- removed. Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 that is now footnote 2 to Spec 2.
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