Datasheet

Electrical Characteristics
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
13
3.7.1 Input Value of Pins During POR Dependent on V
DD33
When powering up the device, V
DD33
must not lag the latest V
DDSYN
or RESET power pin (V
DDEH6
) by
more than the V
DD33
lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. V
DD33
can lag V
DDSYN
or the RESET power
pin (V
DDEH6
), but cannot lag both by more than the V
DD33
lag specification. This V
DD33
lag specification
applies during power up only. V
DD33
has no lead or lag requirements when powering down.
3.7.2 Power-Up Sequence (V
RC33
Grounded)
The 1.5 V V
DD
power supply must rise to 1.35 V before the 3.3 V V
DDSYN
power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, V
DD
must be within specification before the 3.3 V POR and the RESET
POR negate.
Figure 3. Power-Up Sequence (V
RC33
Grounded)
3.7.3 Power-Down Sequence (V
RC33
Grounded)
The only requirement for the power-down sequence with V
RC33
grounded is if V
DD
decreases to less than
its operating range, V
DDSYN
or the RESET power must decrease to less than 2.0 V before the V
DD
power
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See
Table 6, footnote 1.
V
DDSYN
and RESET Power
V
DD
2.0 V
1.35 V
V
DD
must reach 1.35 V before V
DDSYN
and the RESET power reach 2.0 V