Datasheet

MPC5566 Microcontroller Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor20
3.9 Oscillator and FMPLL Electrical Characteristics
Table 12. FMPLL Electrical Specifications
(V
DDSYN
= 3.0–3.6 V; V
SS
= V
SSSYN
= 0.0 V; T
A
= T
L
to T
H
)
Spec Characteristic Symbol Minimum Maximum Unit
1
PLL reference frequency range:
1
Crystal reference
External reference
Dual controller (1:1 mode)
f
ref_crystal
f
ref_ext
f
ref_1:1
8
8
24
20
20
f
sys
 2
MHz
2 System frequency
2
f
sys
f
ICO(MIN)
 2
RFD
f
MAX
3
MHz
3 System clock period t
CYC
—1  f
sys
ns
4 Loss of reference frequency
4
f
LOR
100 1000 kHz
5 Self-clocked mode (SCM) frequency
5
f
SCM
7.4 17.5 MHz
6
EXTAL input high voltage crystal mode
6
All other modes
[dual controller (1:1), bypass, external reference]
V
IHEXT
V
IHEXT
V
XTAL
+ 0.4 V
(V
DDE5
 2) + 0.4 V
—
—
V
V
7
EXTAL input low voltage crystal mode
7
All other modes
[dual controller (1:1), bypass, external reference]
V
ILEXT
V
ILEXT
—
—
V
XTAL
– 0.4 V
(V
DDE5
2) – 0.4 V
V
V
8 XTAL current
8
I
XTAL
26mA
9 Total on-chip stray capacitance on XTAL C
S_XTAL
—1.5pF
10 Total on-chip stray capacitance on EXTAL C
S_EXTAL
—1.5pF
11
Crystal manufacturer’s recommended capacitive
load
C
L
Refer to crystal
specification
Refer to crystal
specification
pF
12
Discrete load capacitance to connect to EXTAL C
L_EXTAL
—
(2  C
L
) – C
S_EXTAL
– C
PCB_EXTAL
9
pF
13
Discrete load capacitance to connect to XTAL C
L_XTAL
—
(2  C
L
) – C
S_XTAL
– C
PCB_XTAL
9
pF
14 PLL lock time
10
t
lpll
— 750 s
15
Dual controller (1:1) clock skew
(between CLKOUT and EXTAL)
11, 12
t
skew
–2 2 ns
16 Duty cycle of reference
t
DC
40 60 %
17 Frequency unLOCK range f
UL
–4.0 4.0 % f
SYS
18 Frequency LOCK range f
LCK
–2.0 2.0 % f
SYS