Datasheet

Electrical Characteristics
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
21
19
CLKOUT period jitter,
measured at f
SYS
max:
13, 14
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
C
JITTER
—
—
5.0
0.01
%
f
CLKOUT
20
Frequency modulation range limit
15
(do not exceed f
sys
maximum)
C
MOD
0.8 2.4
%f
SYS
21
ICO frequency
f
ico
= [f
ref_crystal
 (MFD + 4)] (PREDIV + 1)
16
f
ico
= [f
ref_ext
 (MFD + 4)] (PREDIV + 1)
f
ico
48 f
MAX
MHz
22 Predivider output frequency (to PLL) f
PREDIV
420
17
MHz
1
Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within ± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2
All internal registers retain data at 0 Hz.
3
Up to the maximum frequency rating of the device (refer to Ta bl e 1).
4
Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
5
The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f
LOR
. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
6
Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (V
extal
– V
xtal
) must be  400 mV for the oscillator’s comparator to produce the output clock.
7
Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (V
xtal
–V
extal
) must be  400 mV for the oscillator’s comparator to produce the output clock.
8
I
xtal
is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
9
C
PCB_EXTAL
and C
PCB_XTAL
are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
10
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
11
PLL is operating in 1:1 PLL mode.
12
V
DDE
= 3.0–3.6 V.
13
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
DDSYN
and V
SSSYN
and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
14
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
15
Modulation depth selected must not result in f
sys
value greater than the f
sys
maximum specified value.
16
f
sys
= f
ico
 (2
RFD
).
17
Maximum value for dual controller (1:1) mode is (f
MAX
2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).
Table 12. FMPLL Electrical Specifications (continued)
(V
DDSYN
= 3.0–3.6 V; V
SS
= V
SSSYN
= 0.0 V; T
A
= T
L
to T
H
)
Spec Characteristic Symbol Minimum Maximum Unit