Datasheet

Electrical Characteristics
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
39
3.13.7 eMIOS Timing
Figure 17. eMIOS Timing
3.13.8 DSPI Timing
Table 25. eMIOS Timing
1
1
eMIOS timing specified at: V
DDEH
= 3.0–5.25 V and T
A
= T
L
to T
H
.
Spec Characteristic Symbol Min. Max. Unit
1 eMIOS input pulse width t
MIPW
4—t
CYC
2 eMIOS output pulse width t
MOPW
1
2
2
This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).
—t
CYC
Table 26. MPC5566 DSPI Timing
1, 2
Spec
Characteristic
Symbol
80 MHz 112 MHz 132 MHz 144 MHz
Unit
Min Max Min Max Min Max Min Max
1 SCK cycle time
3, 4
t
SCK
24.4 ns 2.9 ms 17.5 ns 2.1 ms 14.8 ns 1.8 ms 13.6 ns 1.6 ms —
2 PCS to SCK delay
5
t
CSC
23 — 15 — 13 — 12 — ns
3 After SCK delay
6
t
ASC
22 — 14 — 12 — 11 — ns
4
SCK duty cycle
t
SDC
(t
SCK
 2)
– 2 ns
(t
SCK
 2)
+ 2 ns
(t
SCK
 2)
– 2 ns
(t
SCK
 2)
+ 2 ns
(t
SCK
 2)
– 2 ns
(t
SCK
 2)
+ 2 ns
(t
SCK
 2)
– 2 ns
(t
SCK
 2)
+ 2 ns
ns
5
Slave access time
(SS
active to SOUT driven)
t
A
— 25 — 25 — 25 — 25 ns
6
Slave SOUT disable time
(SS
inactive to SOUT Hi-Z, or
invalid)
t
DIS
— 25 — 25 — 25 — 25 ns
7PCSx to PCSS time t
PCSC
4—4—4—4—ns
1
2
eMIOS
output
eMIOS input