Datasheet
MPC5566 Microcontroller Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor40
8PCSS
to PCSx time t
PASC
5—5—5—5—ns
9
Data setup time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
7
Master (MTFE = 1, CPHA = 1)
t
SUI
20
2
–4
20
—
—
—
—
20
2
3
20
—
—
—
—
20
2
6
20
—
—
—
—
20
2
7
20
—
—
—
—
ns
ns
ns
ns
10
Data hold time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
7
Master (MTFE = 1, CPHA = 1)
t
HI
–4
7
21
–4
—
—
—
—
–4
7
14
–4
—
—
—
—
–4
7
12
–4
—
—
—
—
–4
7
11
–4
—
—
—
—
ns
ns
ns
ns
11
Data valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t
SUO
—
—
—
—
5
25
18
5
—
—
—
—
5
25
14
5
—
—
—
—
5
25
13
5
—
—
—
—
5
25
12
5
ns
ns
ns
ns
12
Data hold time for outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t
HO
–5
5.5
8
–5
—
—
—
—
–5
5.5
4
–5
—
—
—
—
–5
5.5
3
–5
—
—
—
—
–5
5.5
1
–5
—
—
—
—
ns
ns
ns
ns
1
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of S or SH have
an additional delay based on the slew rate. DSPI timing is specified at V
DDEH
= 3.0–5.25 V, T
A
= T
L
to T
H
, and CL = 50 pF with SRC = 0b11.
2
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and
135 MHz parts allow for 132 MHz system clock + 2% FM; and 147 MHz parts allow for 144 MHz system clock + 2% FM.
3
The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
4
The actual minimum SCK cycle time is limited by pad performance.
5
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
6
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
7
This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
Table 26. MPC5566 DSPI Timing
1,
2
(continued)
Spec
Characteristic
Symbol
80 MHz 112 MHz 132 MHz 144 MHz
Unit
Min Max Min Max Min Max Min Max