Datasheet

Electrical Characteristics
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
45
3.13.9 eQADC SSI Timing
Figure 27. EQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics
Spec Rating Symbol Minimum Typical Maximum Unit
2 FCK period (t
FCK
= 1  f
FCK
)
1, 2
1
SS timing specified at V
DDEH
= 3.0–5.25 V, T
A
= T
L
to T
H
, and CL = 25 pF with SRC = 0b11. Maximum operating frequency
varies depending on track delays, master pad delays, and slave pad delays.
2
FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.
t
FCK
2— 17t
SYS_CLK
3 Clock (FCK) high time t
FCKHT
t
SYS_CLK
 6.5 — 9  (t
SYS_CLK
 6.5) ns
4 Clock (FCK) low time t
FCKLT
t
SYS_CLK
 6.5 — 8  (t
SYS_CLK
 6.5) ns
5 SDS lead / lag time t
SDS_LL
–7.5 — +7.5 ns
6 SDO lead / lag time t
SDO_LL
–7.5 — +7.5 ns
7 EQADC data setup time (inputs) t
EQ_SU
22 — — ns
8 EQADC data hold time (inputs) t
EQ_HO
1— — ns
1st (MSB) 2nd
25th
26th
1st (MSB) 2nd 25th 26th
8
7
56
45
4
2
3
FCK
SDS
SDO
External device data sample at
SDI
EQADC data sample at
FCK falling-edge
FCK rising-edge