Datasheet

MPC5566 Microcontroller Data Sheet, Rev. 3

Electrical Characteristics

Freescale Semiconductor46

3.14 Fast Ethernet AC Timing Specifications

Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic

(TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC

signals are independent of the system clock frequency (part speed designation).

3.14.1 MII FEC Receive Signal Timing

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK

The receive functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz plus one percent.

There is no minimum frequency requirement. The processor clock frequency must exceed four times the

FEC_RX_CLK frequency.

Table 28 lists MII FEC receive channel timings.

Figure 28 shows MII FEC receive signal timings listed in Table 28.

Figure 28. MII FEC Receive Signal Timing Diagram

Table 28. MII FEC Receive Signal Timing

Spec Characteristic Min. Max Unit

1 FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup 5 — ns

2 FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold 5 — ns

3 FEC_RX_CLK pulse-width high 35% 65% FEC_RX_CLK period

4 FEC_RX_CLK pulse-width low 35% 65% FEC_RX_CLK period

FEC_RX_CLK (input)

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER