Datasheet

Revision History for the MPC5566 Data Sheet
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
57
5.3 Information Changed Between Revisions 0.0 and 1.0
The following table lists the global changes made throughout the document, as well as the changes to
sections of text not contained in a figure or table.
Table 34. Global and Text Changes Between Rev. 0.0 and 1.0
Location Description of Changes
Global Changes
• Third paragraph and throughout the document, replaced:
• kilobytes with KB.
• megabytes with MB.
• Put overbars on the following signals: BB
, BG, BR, BDIP, OE, TA, TEA, TS,
• Changed WE[0:3]/BE[0:3] to WE/BE[0:3].
• Added a 144 MHz system frequency option for the MPC5566 microcontroller.
Section 1, “Overview”:
• First paragraph, text changed from “ based on the PowerPC Book E architecture” to “built on the Power
Architecture embedded technology.”
• Second paragraph: Changed terminology from PowerPC Book E architecture to Power Architecture terminology.
• Added new fourth paragraph about VLE feature.
• Paragraph nine: changed “the MPC5566 has an on-chip 20-channel enhanced queued analog-to-digital
converter (eQADC)” to “has an on-chip 40-channel dual enhanced queued”
• Added paragraph about the Fast Ethernet Controller directly after the System Integration Unit paragraph.
• Added the sentence directly preceding Table 1: ‘Unless noted in this data sheet, all specifications apply from
T
L
to T
H
.’
3.7.1, 3.7.2 and 3.7.3: Reordered sections resulting in the following order and section renumbering:
• Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33,” then
• Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” then
• Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).
Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33,” changed:
From:
‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG
are not treated as ones
(1s) when POR negates, V
DD33
must not lag V
DDSYN
and the RESET pin power (V
DDEH6
) when powering the
device by more than the V
DD33
lag specification in Ta ble 6 . V
DD33
individually can lag either V
DDSYN
or the
RESET power pin (V
DDEH6
) by more than the V
DD33
lag specification. V
DD33
can lag one of the V
DDSYN
or
V
DDEH6
supplies, but cannot lag both by more than the V
DD33
lag specification. This V
DD33
lag specification only
applies during power up. V
DD33
has no lead or lag requirements when powering down.’
To:
‘When powering the device, V
DD33
must not lag V
DDSYN
and the RESET power pin (V
DDEH6
) by more than the
V
DD33
lag specification listed in Table 6. This avoids accidentally selecting the bypass clock mode because the
internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state
when POR negates. V
DD33
can lag V
DDSYN
or the RESET power pin (V
DDEH6
), but cannot lag both by more than
the V
DD33
lag specification. This V
DD33
lag specification only applies during power up. V
DD33
has no lead or lag
requirements when powering down.’