Datasheet

MPC5566 Microcontroller Data Sheet, Rev. 3
Revision History for the MPC5566 Data Sheet
Freescale Semiconductor60
Tabl e 5, ESD Characteristics: Added (Electromagnetic Static Discharge) in the table title.
Tabl e 6, VCR/POR Electrical Specifications:
• Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET
before V
POR15
, V
POR33
, and V
POR5
negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions
as specified in Table 9 DC Electrical Specifications. On power down, assert RESET
before any power supplies
fall outside the operating conditions and until the internal POR asserts.
• Subscript all symbol names that appear after the first underscore character.
• Specs 7 and 10: added ‘at Tj ‘ at the end of the first line in the second column: Characteristic.
• Removed ‘Tj ‘ after ‘150 C’ in the last line, second column: Characteristic.
• Spec 10, second column, second line:
Added cross-reference to footnote 6: ‘I
VRCCTL
is measured at the following conditions: V
DD
= 1.35 V, V
RC33
=3.1
V, V
VRCCTL
= 2.2 V.’ Changed ‘(@ V
DD
= 1.35 V, f
sys
= f
MAX
)‘ to ‘(@ f
sys
= f
MAX
).’
• Footnote 10: Deleted ‘Preliminary value. Final specification pending characterization.”
• Added to Spec 2:
3.3 V (V
DDSYN
) POR negated (ramp down) Min 0.0 Max 0.30 V
3.3 V (V
DDSYN
) POR asserted (ramp up) Min 0.0 Max 0.30 V
• Added new footnote 1 to both lines in Spec 3: “ V
IL_S
(Table 9, Spec 15) is guaranteed to scale with V
DDEH6
down
to V
POR5
.
• Spec 5: Changed old Footnote 1 (now footnote 2): ‘User must be able to supply full operating current for the 1.5V
supply when the 3.3V supply reaches this range.” to ‘Supply full operating current for the 1.5 V supply when the
3.3 V supply reaches this range.”
• Spec 3: Added new footnote 3 for both lines: ‘It is possible to reach the current limit during ramp up--do not treat
this event as a short circuit current.’
• Spec 10:
• Changed the minimum values of: -40 C = 60; 25 C = 65.
• Added old footnote 5 new footnote 6.
• Added a new footnote 7, ‘Refer to Tab le 1 for the maximum operating frequency.’
• Rewrote old footnote 7(new footnote 9) to: Represents the worst-case external transistor BETA. It is measured
on a per part basis and calculated as (I
DD
 I
VRCCTL
).
• Deleted old footnote 8: ‘Preliminary value. Final specification pending characterization.’
Tabl e 7, Power Sequence Pin Status for Fast Pads:
• Changed title to Pin Status for Fast Pads During the Power Sequence
• Changed preceding paragraph
From: Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive
current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Prior to exiting
POR, the pads are in a high impedance state (Hi-Z).
To: There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies
are powered.
• Deleted the ‘Comment’ column.
• Added a POR column after the V
DD
column.
• Added row 2:’ V
DDE
, Low, Low, Asserted, High’ and row 5: V
DDE
, V
DD33
, V
DD
, Asserted, Hi-Z.
Tabl e 8, Power Sequence Pin Status for Medium/Slow Pads:
• Changed title to Pin Status for Medium and Slow Pads During the Power Sequence
• Updated preceding paragraph.
• Deleted the ‘Comment’ column.
• Added a POR column after the V
DD
column.
• Added row 3:’ V
DDEH
, V
DD
, Asserted, Hi-Z.’
Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued)
Location Description of Changes