Datasheet

MPC5566 Microcontroller Data Sheet, Rev. 3
Revision History for the MPC5566 Data Sheet
Freescale Semiconductor62
Tabl e 9, DC Electrical Specifications (continued)
• Spec 27e, Operating current 1.5 V supplies @ 147 MHz:
Added maximum values for 8-way cache: all with footnote 11.
-- 1.65 typical = 650,
-- 1.35 typical = 530,
-- 1.65 high = 820,
-- 1.35 high = 650.
Added 4-way cache: all with footnote 11.
-- 1.65 high = 720
-- 1.35 high = 585
• Spec 28: Changed 132 MHz to f
MAX
MHz.
• Spec 29: Deleted @ 132 MHz.
• Corrected footnote 3 to read: If standby operation is not required, connect the V
STBY
to ground.
• Combined old footnotes 11 and 12 for new footnote 6 and added to specs 27a, b, and c on the 8-way cache line
that reads: Eight-way cache enabled (L1CSR0[CORG] = 0b0).
• Deleted footnotes 12 and 13 about preliminary specifications and specification pending characterization.
Figure 2, Added figure to show interpolated IDD
STBY
values listed in Ta ble 9 .
Tabl e 12 , FMPLL Electrical Characteristics:
• Added (T
A
= T
L
– T
H
) to the end of the second line in the table title.
• Spec 1, footnote 1 in column 2: ‘PLL reference frequency range’: Changed to read ‘Nominal crystal and external
reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within
± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.‘
• Specs 12 and 13: Grouped (2 x Cl).
• Spec 21, column 2: Changed f
ref_crystal
to f
ref
in ICO frequency equation, and
added the same equation but substituted f
ref_ext
for f
ref
for the external reference clock, giving:
f
ico
= [ f
ref_crystal
 (MFD + 4) ] (PREDIV + 1)
f
ico
= [ f
ref_ext
 (MFD + 4) ] (PREDIV + 1)
• Spec 21, column 4, Max: Deleted old footnote 18 that reads:
The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the CMPLL
synthesizer control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001).
Therefore, for a 40 MHz maximum device (system frequency), program the FMPLL to generate 80 MHz at the
ICO output and then divide-by-two the RFD to provide the 40 MHz system clock.’
• Spec 21: Changed column 5 from ‘f
SYS
’ MHz’ to: ‘f
MAX
’.
• Spec 22: Changed column 4, Max Value from f
MAX
to 20, and added footnote 17 to read, ‘Maximum value for
dual controller (1:1) mode is (f
MAX
2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’
Tabl e 13 , eQADC Conversion Specifications:
Added (T
A
= T
L
– T
H
) to the table title.
Tabl e 14 , Flash Program and Erase Specifications:
• Added (T
A
= T
L
– T
H
) to the table title.
• Specs 7, 8, 9, and 10 Inserted new values for the H7Fa Flash pre-program and erase times and used the previous
values for Typical values.
-- 48 KB: from 340 to 345
-- 64 KB: from 400 to 415
• Spec 8, 128KB block pre-program and erase time, Max column value from 15,000 to 7,500.
• Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.
• Footnote 2: Changed from: ‘Initial factory condition: 100program/erase cycles, 25
o
C, typical supply voltage,
80 MHz minimum system frequency.‘ To: ‘Initial factory condition: 100program/erase cycles, 25
o
C, using a
typical supply voltage measured at a minimum system frequency of 80 MHz.’
Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued)
Location Description of Changes