Freescale Semiconductor Document Number: MPC8241EC Rev. 10, 02/2009 Technical Data MPC8241 Integrated Processor Hardware Specifications The MPC8241 combines a PowerPC™ MPC603E core with a PCI bridge so that system designers can rapidly design systems using peripherals designed for PCI and other standard interfaces. Also, a high-performance memory controller supports various types of ROM and SDRAM.
Overview MPC8241 Processor Core Block Additional Features: • Prog I/O with Watchpoint • JTAG/COP Interface • Power Management Processor PLL (64-Bit) Two-Instruction Fetch Branch Processing Unit (BPU) Instruction Unit (64-Bit) Two-Instruction Dispatch System Register Unit (SRU) Integer Unit (IU) FloatingPoint Unit (FPU) Load/Store Unit (LSU) 64-Bit Data MMU Instruction MMU 16-Kbyte Instruction Cache 16-Kbyte Data Cache Peripheral Logic Bus Peripheral Logic Block Message Unit (with I2O) DMA C
Features The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART), memory controller, DMA controller, PIC interrupt controller, a message unit (and I2O interface), and an I2C controller. The processor core is a full-featured, high-performance processor with floating-point support, memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features.
Features – – – – – – – – Write buffering for PCI and processor accesses Normal parity, read-modify-write (RMW), or ECC Data-path buffering between memory interface and processor Low-voltage TTL logic (LVTTL) interfaces 272 Mbytes of base and extended ROM/Flash/PortX space Base ROM space for 8-bit data path or same size as the SDRAM data path (32- or 64-bit) Extended ROM space for 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port usi
General Parameters • • 3 — I2C controller with full master/slave support that accepts broadcast messages — Programmable interrupt controller (PIC) – Five hardware interrupts (IRQs) or 16 serial interrupts – Four programmable timers with cascade — Two (dual) universal asynchronous receiver/transmitters (UARTs) — Integrated PCI bus and SDRAM clock generation — Programmable PCI bus and memory interface output drivers System level performance monitor facility Debug features — Memory attribute and PCI attribu
Electrical and Thermal Characteristics 4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8241. 4.1 DC Electrical Characteristics This section covers ratings, conditions, and other characteristics. 4.1.1 Absolute Maximum Ratings This section describes the MPC8241 DC electrical characteristics. Table 1 provides the absolute maximum ratings. Table 1.
Electrical and Thermal Characteristics 4.1.2 Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8241. Table 2. Recommended Operating Conditions 1 Characteristic Supply voltage I/O buffer supply for PCI and standard; supply voltages for memory bus drivers Symbol Recommended Value Unit Notes VDD 1.8 ± 100 mV V 2 V 2 GVDD_OVDD 3.3 ± 0.3 CPU PLL supply voltage AVDD 1.8 ± 100 mV PLL supply voltage—peripheral logic AV DD2 1.
Electrical and Thermal Characteristics DC Power Supply Voltage Figure 2 shows supply voltage sequencing and separation cautions. LVDD @ 5 V 5V 6 3.3 V 6 GVDD_OVDD/(LV DD @ 3.
Electrical and Thermal Characteristics Figure 3 shows the undershoot and overshoot voltage of the memory interface. 4V GVDD_OV DD + 5% GVDD_OVDD VIH VIL GND/GNDRING GND/GNDRING – 0.3 V GND/GNDRING – 1.0 V Not to Exceed 10% of tSDRAM_CLK Figure 3. Overshoot/Undershoot Voltage Figure 4 and Figure 5 show the undershoot and overshoot voltage of the PCI interface for the 3.3- and 5-V signals, respectively. 11 ns (Min) +7.1 V Overvoltage Waveform 7.1 Vp-to-p (Min) 4 ns (Max) 0V 4 ns (Max) 62.5 ns +3.
Electrical and Thermal Characteristics 11 ns (Min) +11 V 11 V p-to-p (Min) Overvoltage Waveform 4 ns (Max) 0V 4 ns (Max) 62.5 ns +5.25 V 10.75 V p-to-p (Min) Undervoltage Waveform –5.5 V Figure 5. Maximum AC Waveforms for 5-V Signaling 4.2 DC Electrical Characteristics Table 3 provides the DC electrical characteristics for the MPC8241 at recommended operating conditions. Table 3.
Electrical and Thermal Characteristics Table 3. DC Electrical Specifications (continued) Characteristics Capacitance Conditions Vin = 0 V, f = 1 MHz Symbol Min Max Unit Cin — 16.0 pF Notes Notes: 1. See Table 16 for pins with internal pull-up resistors. 2. All grounded pins are connected together. 3. Leakage current is measured on input and output pins in the high-impedance state.
Electrical and Thermal Characteristics 4.3 Power Characteristics Table 5 provides preliminary estimated power consumption data for the MPC8241. Table 5. Preliminary Power Consumption PCI Bus Clock/Memory Bus Clock CPU Clock Frequency (MHz) Mode 33/100/200 66/100/200 Unit Notes 33/66/133 33/66/166 33/66/200 66/66/ 266 66/133/ 266 Typical 0.7 0.8 1.0 1.0 1.0 1.5 1.8 W 1, 5 Max—CFP 0.8 1.0 1.2 1.3 1.3 1.9 2.1 W 1, 2 Max—INT 0.8 0.9 1.0 1.2 1.2 1.6 1.8 W 1, 3 Doze 0.
Electrical and Thermal Characteristics 4.4 Thermal Characteristics Table 6 provides the package thermal characteristics for the MPC8241. For details, see Section 7.7, “Thermal Management.” Table 6.
Electrical and Thermal Characteristics Table 7 provides the operating frequency information for the MPC8241 at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V. Table 7. Operating Frequency 166 MHz 200 MHz Characteristic 266 MHz VDD/AVDD/AVDD2 = 1.
Electrical and Thermal Characteristics Table 8. Clock AC Timing Specifications (continued) At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V Num 21 Characteristics and Conditions OSC_IN frequency stability Min Max Unit — 100 ppm Notes Notes: 1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 through 2.4 V. 2. Specification value at maximum frequency of operation. 3.
Electrical and Thermal Characteristics Register settings that define each DLL mode are shown in Table 9. Table 9.
Electrical and Thermal Characteristics 30 27.5 Tclk SDRAM_SYNC_OUT Period (ns) 25 22.5 20 17.5 15 12.5 10 7.5 0 1 2 3 4 5 Tloop Propagation Delay Time (ns) Figure 7. DLL Locking Range Loop Delay versus Frequency of Operation for DLL_Extend=0 and Normal Tap Delay MPC8241 Integrated Processor Hardware Specifications, Rev.
Electrical and Thermal Characteristics 30 27.5 Tclk SDRAM_SYNC_OUT Period (ns) 25 22.5 20 17.5 15 12.5 10 7.5 0 1 2 3 4 5 Tloop Propagation Delay Time (ns) Figure 8. DLL Locking Range Loop Delay versus Frequency of Operation for DLL_Extend=1 and Normal Tap Delay MPC8241 Integrated Processor Hardware Specifications, Rev.
Electrical and Thermal Characteristics 30 27.5 Tclk SDRAM_SYNC_OUT Period (ns) 25 22.5 20 17.5 15 12.5 10 7.5 0 1 2 3 4 5 Tloop Propagation Delay Time (ns) Figure 9. DLL Locking Range Loop Delay versus Frequency of Operation for DLL_Extend=0 and Max Tap Delay MPC8241 Integrated Processor Hardware Specifications, Rev.
Electrical and Thermal Characteristics 30 27.5 Tclk SDRAM_SYNC_OUT Period (ns) 25 22.5 20 17.5 15 12.5 10 7.5 0 1 2 3 4 5 Tloop Propagation Delay Time (ns) Figure 10. DLL Locking Range Loop Delay versus Frequency of Operation for DLL_Extend=1 and Max Tap Delay 4.5.2 Input AC Timing Specifications Table 10 provides the input AC timing specifications at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V. See Figure 11 and Figure 12. Table 10.
Electrical and Thermal Characteristics Table 10. Input AC Timing Specifications (continued) Num Characteristic Min Max Unit Notes ns 2, 3, 6 10b0 Tap 0, register offset <0x77>, bits 5:4 = 0b00 2.6 — 10b1 Tap 1, register offset <0x77>, bits 5:4 = 0b01 1.9 — 10b2 Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default) 1.2 — 10b3 Tap 3, register offset <0x77>, bits 5:4 = 0b11 0.5 — 10c PIC miscellaneous debug input signals valid to sys_logic_clk (input setup) 3.
Electrical and Thermal Characteristics PCI_SYNC_IN VM sys_logic_clk VM VM VM Tos SDRAM_SYNC_IN (after DLL locks) Shown in 2:1 Mode VM 10b-d 11a 13b 12b-d 2.0 V 2.0 V 0.8 V 0.8 V 14b Memory Inputs/Outputs Output Timing Notes: VM = Midpoint voltage (1.4 V). 10b-d = Input signals valid timing. 11a = Input hold time of SDRAM_SYNC_IN to memory. 12b-d = sys_logic_clk to output valid timing. 13b = Output hold time for non-PCI signals.
Electrical and Thermal Characteristics Figure 13 shows the input timing diagram for mode select signals. VM HRST_CPU/HRST_CTRL 10e 11b 2.0 V Mode Pins 0.8 V VM = Midpoint Voltage (1.4 V) Figure 13. Input Timing Diagram for Mode Select Signals 4.5.3 Output AC Timing Specification Table 11 provides the processor bus AC timing specifications for the MPC8241 at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V (see Figure 11).
Electrical and Thermal Characteristics Table 11. Output AC Timing Specifications (continued) Num 14b Characteristic sys_logic_clk to output high impedance (for all others) Min Max Unit Notes — 4.0 ns 2 Notes: 1. All PCI signals are measured from GVDD_OVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 × GVDD_OVDD or 0.615 × GV DD_OVDD of the signal in question for 3.3 V PCI signaling levels. See Figure 12. 2.
Electrical and Thermal Characteristics OVDD/2 PCI_SYNC_IN 12a2, 7.0 ns for 33 MHz PCI PCI_HOLD_DEL = 10 OVDD/2 13a2, 2.1 ns for 33 MHz PCI PCI_HOLD_DEL = 10 PCI Inputs/Outputs 33 MHz PCI 12a0, 6.0 ns for 66 MHz PCI PCI_HOLD_DEL = 00 13a0, 1 ns for 66 MHz PCI PCI_HOLD_DEL = 00 PCI Inputs/Outputs 66 MHz PCI As PCI_HOLD_DEL Values Decrease PCI Inputs and Outputs As PCI_HOLD_DEL Values Increase Note: Diagram not to scale. Output Valid Output Hold Figure 15.
Electrical and Thermal Characteristics Table 12. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 5%. Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 2 Input current each I/O pin (input voltage is between 0.1 × OVDD and 0.9 × OVDD(max) II –10 10 μA 3 Capacitance for each I/O pin CI — 10 pF Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2.
Electrical and Thermal Characteristics Table 13. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 12). Parameter Symbol 1 Min Max Unit Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 × OVDD — V Note: 1.
Electrical and Thermal Characteristics Figure 17 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2DVKH tI2CL tI2KHKL tI2CF tI2SXKL tI2CR SCL tI2SXKL S tI2CH tI2DXKL,tI2OVKL tI2SVKH tI2PVKH Sr P S Figure 17. I2C Bus AC Timing Diagram 4.7 PIC Serial Interrupt Mode AC Timing Specifications Table 14 provides the PIC serial interrupt mode AC timing specifications for the MPC8241 at recommended operating conditions (see Table 2) with GVDD_OVDD = 3.3 V ± 5% and LVDD = 3.3 V ± 0.3 V.
Electrical and Thermal Characteristics sys_logic_clk VM VM VM 3 S_CLK 4 VM VM 5 4 S_FRAME VM VM S_RST Figure 18. PIC Serial Interrupt Mode Output Timing Diagram VM S_CLK 7 6 S_INT Figure 19. PIC Serial Interrupt Mode Input Timing Diagram 4.7.1 IEEE 1149.1 (JTAG) AC Timing Specifications Table 15 provides the JTAG AC timing specifications for the MPC8241 while in the JTAG operating mode at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V.
Electrical and Thermal Characteristics Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) Num Characteristic Min Max Unit Notes 11 TMS, TDI data hold time 15 — ns — 12 TCK to TDO data valid 0 15 ns — 13 TCK to TDO high impedance 0 15 ns — Notes: 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Nontest (other than TDI and TMS) signal input timing with respect to TCK. 3. Nontest (other than TDO) signal output timing with respect to TCK.
Package Description TCK 10 TDI, TMS 11 Input Data Valid 12 TDO Output Data Valid 13 TDO Figure 23. Test Access Port Timing Diagram 5 Package Description This section details package parameters, pin assignments, and dimensions. 5.1 Package Parameters for the MPC8241 The MPC8241 uses a 25 mm × 25 mm, cavity up, 357-pin plastic ball grid array (PBGA) package. The package parameters are as follows. Package outline 25 mm × 25 mm Interconnects 357 Pitch 1.
Package Description 5.2 Pin Assignments and Package Dimensions Figure 24 shows the top surface, side profile, and pinout of the MPC8241, 357 PBGA ZP package. Note that this is available for Rev. B parts only. 4X 0.2 D A C 0.20 C NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM C. 0.25 C E2 E 0.35 C D2 TOP VIEW MILLIMETERS DIM MIN MAX A --2.05 A1 0.50 0.70 A2 0.95 1.35 A3 0.
Package Description Figure 25 shows the top surface, side profile, and pinout of the MPC8241, 357 PBGA ZQ and VR packages. Figure 25. MPC8241 Package Dimensions and Pinout Assignments (ZQ and VR Packages) MPC8241 Integrated Processor Hardware Specifications, Rev.
Package Description 5.3 Pinout Listings Table 16 provides the pinout listing for the MPC8241, 357 PBGA package. Table 16.
Package Description Table 16.
Package Description Table 16.
Package Description Table 16.
Package Description Table 16. MPC8241 Pinout Listing (continued) Pin Type Power Supply Output Driver Type Notes I/O GVDD_OVDD — 1, 5, 20 T13 Output GVDD_OVDD DRV_PCI 1, 19 DA[12:13] M16 N16 Output GVDD_OVDD DRV_STD_MEM 19 DA[14:15] B6 D8 Output GVDD_OVDD DRV_MEM_CTRL 1, 19 Signal Name DA[10:6]/ PLL_CFG[0:4] DA[11] Package Pin Number N3 N2 N1 M4 M3 Notes: 1.
PLL Configuration 6 PLL Configuration The PLL_CFG[0:4] are configured by the internal PLLs. For a specific PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO) frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations are shown in Table 17 and Table 18. Table 17.
PLL Configuration Table 17.
PLL Configuration Table 18. PLL Configurations (266-MHz Parts) (continued) 266-MHz Part 9 Ref 2 PLL_ CFG[0:4] 10,11 6 0011013 7 (Rev. B) 0011112 7 (Rev. D) 0011114 8 01000 506–661 50–66 9 01001 386 –66 A 01010 B C PCI Clock Input (PCI_SYNC_IN) Range 1 (MHz) Periph Logic/ Mem Bus Clock Range (MHz) Multipliers CPU Clock Range (MHz) PCI-to-Mem (Mem VCO) Bypass 506–661 Bypass 1 (Bypass) 3 (2) 150–198 1 (4) 3 (2) 76–132 152–264 2 (2) 2 (2) 25–295 50–58 225–261 2 (4) 4.
System Design Information Table 18. PLL Configurations (266-MHz Parts) (continued) 266-MHz Part 9 Ref 2 PLL_ CFG[0:4] 10,11 1F 111118 PCI Clock Input (PCI_SYNC_IN) Range 1 (MHz) Periph Logic/ Mem Bus Clock Range (MHz) Not usable Multipliers CPU Clock Range (MHz) PCI-to-Mem (Mem VCO) Mem-to-CPU (CPU VCO) Off Off Notes: 1. Limited by maximum PCI input frequency (66 MHz). 2. Note the impact of the relevant revisions for modes 7 and 1E. 3. Limited by minimum memory VCO frequency (132 MHz). 4.
System Design Information Place the circuits as closely as possible to the respective input signal pins to minimize noise coupled from nearby circuits. Routing from the capacitors to the input signal pins should be as direct as possible with minimal inductance of vias. VDD 10 Ω AV DD or AVDD 2 2.2 µF 2.2 µF GND Low ESL Surface Mount Capacitors Figure 26. PLL Power Supply Filter Circuit 7.
System Design Information 7.4 Pull-Up/Pull-Down Resistor Requirements The data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and PAR[0:7]. If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31] and PAR[4:7]) are disabled, and their outputs drive logic zeros when they would otherwise be driven.
System Design Information 7.6 JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While the TAP controller can be forced to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
System Design Information MPC8241 From Target Board Sources (if any) SRESET 5 HRESET 13 11 SRESET 5 7 HRST_CPU HRESET 10 kΩ SRESET 5 10 kΩ 10 kΩ HRST_CTRL OV DD OVDD OV DD 10 kΩ OV DD 0Ω8 4 1 2 3 4 6 6 2 7 8 9 10 11 12 KEY 13 No pin 15 16 COP Connector Physical Pin Out 5 15 3 Key 14 4 COP Header 5 TRST VDD_SENSE TRST 7 1 kΩ 10 kΩ OVDD 10 kΩ 10 kΩ CHKSTOP_IN 6 8 TMS 9 1 3 OVDD TDO TDI OVDD OVDD CHKSTOP_IN 6 TMS TDO TDI TCK TCK 7 2 NC 10 NC 12 NC QACK 1 16 No
System Design Information 7.7 Thermal Management This section provides thermal management information for the plastic ball grid array (PBGA) package for air-cooled applications. Depending on the application environment and the operating frequency, a heat sink may be required to maintain junction temperature within specifications. Proper thermal control design primarily depends on the system-level design: heat sink, airflow, and thermal interface material.
Die Junction-to-Ambient Die Junction-to-Ambient Thermal Resistance (C/W) Thermal Resistance (°C/W) System Design Information 50.0 40.0 1s 30.0 2s2p 1s/s ink 20.0 2s2p/s ink 10.0 0.0 0 0.5 1 1.5 2 2.5 Airflow Velocity (m/s) Airflow Velocity (m/s) Figure 29. Die Junction-to-Ambient Resistance The board designer can choose among several types of heat sinks to place on the MPC8241.
System Design Information 7.7.1 Internal Package Conduction Resistance For the PBGA, die-up, packaging technology, shown in Figure 28, the intrinsic conduction thermal resistance paths are as follows: • The die junction-to-case thermal resistance • The die junction-to-ball thermal resistance Figure 30 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
System Design Information Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Specific Thermal Resistance (K-in.2/W) 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) Figure 31. Thermal Performance of Select Thermal Interface Material The board designer can choose among several types of thermal interface.
System Design Information Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 7.7.
Ordering Information where: TT = thermocouple temperature atop the package (°C) ψJT = thermal characterization parameter (°C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package.
Ordering Information 8.1 Part Numbers Fully Addressed by This Document Table 19 provides the Freescale part numbering nomenclature for the MPC8241. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier that may specify special application conditions.
Document Revision History Table 20. Part Numbers Addressed by MPC8241TXXPNS Series (Document No. MPC8241ECSO1AD)) MPC nnnn MPC 8241 T T = Extended temperature spec. –40° to 105°C xx nnn ZQ = thick substrate and thick mold cap PBGA (two layers) 166, 200 @ 1.8 V ± 100 mV x D:1.4 = Rev. ID:0x14 0x80811014 Notes: 1. See Section 5, “Package Description,” for more information on available package types. 2. Processor core frequencies supported by parts addressed by this specification only.
Document Revision History Table 21. Revision History Table (continued) Revision Date Substantive Change(s) 8 12/19/2005 Document—Imported new template and made minor editoral corrections. Section 4.3.1—Before Figure 7, added paragraph for using DLL mode that provides lowest locked tap point read in 0xE3. Section 4.3.2—After Figure 12, added a sentence to introduce Figure 13. Section 4.3.3—After Table 11, added a sentence to introduce Figure 14. Section 4.3.
Document Revision History Table 21. Revision History Table (continued) Revision Date Substantive Change(s) 4 — Section 1.4.1.2—Table 2: Changed note 1. Figure 2: Updated note 2 and removed ‘voltage regulator delay’ label since Section 1.7.2 is being deleted this revision. Also, updated Table 5, note 1 to reflect deletion of Section 1.7.2. Section 1.4.1.3—Table 3: Updated the maximum input capacitance from 15 to 16 pF based on characterization data. Section 1.4.3.
Document Revision History Table 21. Revision History Table (continued) Revision Date Substantive Change(s) 1 — Updated document template. Section 1.4.1.5—Updated driver type names in Table 4 so that they are consistent with the driver types referred to in the MPC8245 Integrated Processor Reference Manual. Added notes 5 and 6 to Table 4. Section 1.4.3.1—Added reference to AN2164 in note 7. Labeled N value in Figures 5 through 8. Section 1.4.3.2—Updated Figure 9 to show Tos.
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