Datasheet

MPC8241 Integrated Processor Hardware Specifications, Rev. 10
28 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 17 shows the AC timing diagram for the I
2
C bus.
Figure 17. I
2
C Bus AC Timing Diagram
4.7 PIC Serial Interrupt Mode AC Timing Specifications
Table 14 provides the PIC serial interrupt mode AC timing specifications for the MPC8241 at
recommended operating conditions (see Table 2) with GV
DD
_OV
DD
= 3.3 V ± 5% and
LV
DD
= 3.3 V ± 0.3 V.
Table 14. PIC Serial Interrupt Mode AC Timing Specifications
Num Characteristic Min Max Unit Notes
1 S_CLK frequency 1/14 SDRAM_SYNC_IN 1/2 SDRAM_SYNC_IN MHz 1
2 S_CLK duty cycle 40 60 % —
3 S_CLK output valid time — 6 ns —
4 Output hold time 0 — ns —
5S_FRAME
, S_RST output valid time — 1 sys_logic_clk period + 6 ns 2
6 S_INT input setup time to S_CLK 1 sys_logic_clk period + 2 — ns 2
7 S_INT inputs invalid (hold time) to S_CLK — 0 ns 2
Notes:
1. See the MPC8245 Integrated Processor Reference Manual for a description of the PIC interrupt control register (ICR) and
S_CLK frequency programming.
2. S_RST, S_FRAME
, and S_INT shown in Figure 18 and Figure 19, depict timing relationships to sys_logic_clk and S_CLK
and do not describe functional relationships between S_RST, S_FRAME
, and S_INT. The MPC8245 Integrated Processor
Reference Manual describes the functional relationships between these signals.
3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;
sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is
implemented and the DLL is locked. See the MPC8245 Integrated Processor Reference Manual for a complete clocking
description.
SrS
SDA
SCL
t
I2CF
t
I2SXKL
t
I2CL
t
I2CH
t
I2DXKL,
t
I2OVKL
t
I2DVKH
t
I2SXKL
t
I2SVKH
t
I2KHKL
t
I2PVKH
t
I2CR
t
I2CF
PS