Datasheet

MPC8241 Integrated Processor Hardware Specifications, Rev. 10
30 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 20 through Figure 23 show the different timing diagrams for JTAG.
Figure 20. JTAG Clock Input Timing Diagram
Figure 21. JTAG TRST
Timing Diagram
Figure 22. JTAG Boundary Scan Timing Diagram
11 TMS, TDI data hold time 15 — ns —
12 TCK to TDO data valid 0 15 ns —
13 TCK to TDO high impedance 0 15 ns —
Notes:
1. TRST
is an asynchronous signal. The setup time is for test purposes only.
2. Nontest (other than TDI and TMS) signal input timing with respect to TCK.
3. Nontest (other than TDO) signal output timing with respect to TCK.
Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)
Num Characteristic Min Max Unit Notes
TCK
22
1
VM
VM
VM
33
VM = Midpoint Voltage
4
5
TRST
TCK
6
7
Input Data Valid
8
9
Output Data Valid
TCK
Data Inputs
Data Outputs
Data Outputs