Datasheet

MPC8241 Integrated Processor Hardware Specifications, Rev. 10
36 Freescale Semiconductor
Package Description
PCI_CLK1/SIN1 U16 Output GV
DD
_OV
DD
DRV_PCI_CLK 5, 14, 24
PCI_CLK2/RTS1
/SOUT2 W18 Output GV
DD
_OV
DD
DRV_PCI_CLK 5, 14
PCI_CLK3/CTS1
/SIN2 V19 Output GV
DD
_OV
DD
DRV_PCI_CLK 5, 14, 24
PCI_CLK4/DA3 V17 Output GV
DD
_OV
DD
DRV_PCI_CLK 5, 14
PCI_SYNC_OUT U17 Output GV
DD
_OV
DD
DRV_PCI_CLK —
PCI_SYNC_IN V18 Input GV
DD
_OV
DD
——
SDRAM_CLK[0:3] D7 B7 C5 A5 Output GV
DD
_OV
DD
DRV_MEM_CTRL 1, 22
SDRAM_SYNC_OUT B4 Output GV
DD
_OV
DD
DRV_MEM_CTRL —
SDRAM_SYNC_IN A4 Input GV
DD
_OV
DD
——
CKO/DA1 L1 Output GV
DD
_OV
DD
DRV_STD_MEM 5
OSC_IN R17 Input GV
DD
_OV
DD
—15
Miscellaneous Signals
HRST_CTRL
M2 Input GV
DD
_OV
DD
—25
HRST_CPU
L4 Input GV
DD
_OV
DD
—25
MCP
K4 Output GV
DD
_OV
DD
DRV_STD_MEM 10, 11, 16
NMI M1 Input GV
DD
_OV
DD
——
SMI
L2 Input GV
DD
_OV
DD
—12
SRESET
/SDMA12 L3 I/O GV
DD
_OV
DD
DRV_MEM_CTRL 5, 12
TBEN/SDMA13 K3 I/O GV
DD
_OV
DD
DRV_MEM_CTRL 5, 12
QACK
/DA0 A3 Output GV
DD
_OV
DD
DRV_STD_MEM 5, 11, 12
CHKSTOP_IN
/SDMA14 K2 I/O GV
DD
_OV
DD
DRV_MEM_CTRL 5, 12
TRIG_IN/RCS2
P18 I/O GV
DD
_OV
DD
—5, 12
TRIG_OUT/RCS3
N18 Output GV
DD
_OV
DD
DRV_STD_MEM 5
MAA[0:2] E17 D17 C18 Output GV
DD
_OV
DD
DRV_STD_MEM 1, 10, 11
MIV
K1 Output GV
DD
_OV
DD
DRV_STD_MEM 23
PMAA[0:1] N19 N17 Output GV
DD
_OV
DD
DRV_STD_MEM 1, 2, 10, 11
PMAA[2] M15 Output GV
DD
_OV
DD
DRV_STD_MEM 1, 2, 10, 11
Test/Configuration Signals
PLL_CFG[0:4]/DA[10:6] N3 N2 N1 M4 M3 I/O GV
DD
_OV
DD
— 1, 5, 20
TEST0
P16 Input GV
DD
_OV
DD
—13, 21
RTC D13 Input GV
DD
_OV
DD
—12
TCK T19 Input GV
DD
_OV
DD
—6, 13
TDI N15 Input GV
DD
_OV
DD
—6, 13
TDO T17 Output GV
DD
_OV
DD
DRV_PCI 23
Table 16. MPC8241 Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Power
Supply
Output
Driver Type
Notes