Datasheet

MPC8241 Integrated Processor Hardware Specifications, Rev. 10
46 Freescale Semiconductor
System Design Information
Figure 27. COP Connector Diagram
HRESET
7
HRST_CPU
HRST_CTRL
From Target
Board Sources
HRESET
13
SRESET
5
SRESET
5
SRESET
5
NC
NC
NC
11
VDD_SENSE
6
5
2
15
3
1 kΩ
10 kΩ
10 kΩ
10 kΩ
OV
DD
OV
DD
OV
DD
OV
DD
CHKSTOP_IN
6
CHKSTOP_IN
6
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP Header
14
4
Key
Notes:
1. QACK
is an output and is not required at the COP header for emulation.
2. RUN/STOP normally on pin 5 of the COP header is not implemented on the MPC8241.
Connect pin 5 of the COP header to OV
DD
with a 1- kΩ pull-up resistor.
3. CKSTP_OUT
normally on pin 15 of the COP header is not implemented on the MPC8241.
Connect pin 15 of the COP header to OV
DD
with a 10-kΩ pull-up resistor.
4. Pin 14 is not physically present on the COP header.
QACK
1
OV
DD
OV
DD
10 kΩ
OV
DD
TRST
7
10 kΩ
OV
DD
10 kΩ
10 kΩ
5. SRESET functions as output SDMA12 in extended ROM mode.
6. CHKSTOP_IN
functions as output SDMA14 in extended ROM mode.
MPC8241
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pin Out
1
7. The COP port and target board should be able to independently assert HRESET and TRST to
.
the processor to fully control the processor as shown.
8. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header through an AND gate to TRST
of the part. If the JTAG interface is not implemented, connect
HRESET
from the target source to TRST of the part through a 0-Ω isolation resistor.
0 Ω
8