Datasheet

MPC8241 Integrated Processor Hardware Specifications, Rev. 10
8 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 2 shows supply voltage sequencing and separation cautions.
Figure 2. Supply Voltage Sequencing and Separation Cautions
GV
DD
_OV
DD
/(LV
DD
@ 3.3 V - - - -)
V
DD
/AV
DD
/AV
DD
2
LV
DD
@ 5 V
Time
3.3 V
5 V
2 V
0
3
6
5
56
2
DC Power Supply Voltage
Reset
Configuration Pins
HRST_CPU
and
HRST_CTRL
PLL
Relock
Time
3
100 µs
Nine External Memory
Asserted 255
External Memory
HRST_CPU and
HRST_CTRL
V
DD
Stable
Power Supply Ramp Up
2
See Note 1
Clock Cycles
3
Clock Cycles Setup Time
4
VM = 1.4 V
One External Memory Clock Cycle
5
Maximum Rise Time Must be Less Than
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.
2. See the Cautions section of Ta bl e 2 for details on this topic.
3. Refer to Ta b le 8 for details on PLL relock and reset signal assertion timing requirements.
4. Refer to Ta b le 1 0 for details on reset configuration pin setup timing requirements.
5. HRST_CPU
/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN
clock cycle for the device to be in the nonreset state.
6. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation
of HRST_CTRL
and HRST_CPU negate in order to be latched.
PLL
6