Freescale Semiconductor MPC8245EC Rev. 10, 08/2007 Technical Data MPC8245 Integrated Processor Hardware Specifications The MPC8245 combines a PowerPC™ MPC603e processor core built on Power Architecture™ technology with a PCI bridge so that system designers can rapidly design systems using peripherals designed for PCI and the other standard interfaces. Also, a high-performance memory controller supports various types of ROM and SDRAM.
Overview MPC8245 Processor Core Block Additional Features: • Prog I/O with Watchpoint • JTAG/COP Interface • Power Management Processor PLL (64-Bit) Two-Instruction Fetch Branch Processing Instruction Unit Unit (BPU) (64-Bit) Two-Instruction Dispatch System Register Unit (SRU) Integer Unit (IU) FloatingPoint Unit (FPU) Load/Store Unit (LSU) 64-Bit Data MMU 16-Kbyte Data Cache Instruction MMU 16-Kbyte Instruction Cache Peripheral Logic Bus Peripheral Logic Block Message Unit (with I2O) DMA Cont
Features The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART), memory controller, DMA controller, PIC interrupt controller, a message unit (and I2O interface), and an I2C controller. The processor core is a full-featured, high-performance processor with floating-point support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and power management features.
Features – – – – – – – – — — — — Write buffering for PCI and processor accesses Normal parity, read-modify-write (RMW), or ECC Data-path buffering between memory interface and processor Low-voltage TTL logic (LVTTL) interfaces 272 Mbytes of base and extended ROM/Flash/PortX space Base ROM space for 8-bit data path or same size as the SDRAM data path (32- or 64-bit) Extended ROM space for 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path PortX: 8-, 16-, 32-, or 64-bit general-purpose
General Parameters • • 3 — Programmable interrupt controller (PIC) – Five hardware interrupts (IRQs) or 16 serial interrupts – Four programmable timers with cascade — Two (dual) universal asynchronous receiver/transmitters (UARTs) — Integrated PCI bus and SDRAM clock generation — Programmable PCI bus and memory interface output drivers System-level performance monitor facility Debug features — Memory attribute and PCI attribute signals — Debug address signals — MIV signal—Marks valid address and data bus
Electrical and Thermal Characteristics 4.1.1 Absolute Maximum Ratings The tables in this section describe the MPC8245 DC electrical characteristics. Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings Characteristic 1 Symbol Range Unit VDD –0.3 to 2.25 V Supply voltage—memory bus drivers GVDD –0.3 to 3.6 V Supply voltage—PCI and standard I/O buffers OVDD –0.3 to 3.6 V AV DD/AVDD 2 –0.3 to 2.25 V LVDD –0.3 to 5.4 V Vin –0.3 to 3.
Electrical and Thermal Characteristics Table 2. Recommended Operating Conditions1 (continued) Characteristic PLL supply voltage—peripheral logic PCI reference Input voltage Symbol Recommended Value Unit Notes AVDD2 1.8/1.9/2.0 V ± V 4, 7, 12 2.0/2.1 V ± V 5, 7, 12 5.0 ± 5% V 2, 10, 11 3.3 ± 0.3 V 3, 10, 11 0 to 3.6 or 5.75 V 2, 3 0 to 3.6 V 6 0 to 105 °C LV DD PCI inputs Vin All other inputs Die-junction temperature Tj Notes: 1.
Electrical and Thermal Characteristics Figure 2 shows supply voltage sequencing and separation cautions. LVDD @ 5 V DC Power Supply Voltage 5V 11 10 3.3 V 11 OVDD/GVDD/(LVDD @ 3.3 V - - - -) 10 2.
Electrical and Thermal Characteristics Figure 3 shows the undershoot and overshoot voltage of the memory interface. VIH VIL 4V GVDD + 5% GVDD GND GND – 0.3 V GND – 1.0 V Not to Exceed 10% of tSDRAM_CLK Figure 3. Overshoot/Undershoot Voltage Figure 4 and Figure 5 show the undershoot and overshoot voltage of the PCI interface for the 3.3- and 5-V signals, respectively. 11 ns (Min) +7.1 V Overvoltage Waveform 7.1 V p-to-p (Min) 4 ns (Max) 0V 4 ns (Max) 62.5 ns +3.6 V Undervoltage Waveform 7.
Electrical and Thermal Characteristics 11 ns (Min) +11 V Overvoltage Waveform 11 V p-to-p (Min) 0V 4 ns (Max) 4 ns (Max) 62.5 ns +5.25 V 10.75 V p-to-p (Min) Undervoltage Waveform –5.5 V Figure 5. Maximum AC Waveforms for 5-V Signaling 4.2 DC Electrical Characteristics Table 3 provides the DC electrical characteristics for the MPC8245 at recommended operating conditions. Table 3.
Electrical and Thermal Characteristics Table 3. DC Electrical Specifications (continued) At recommended operating conditions (see Table 2) Characteristic Capacitance Condition 3 Vin = 0 V, f = 1 MHz Symbol Min Max Unit Cin — 16.0 pF Notes Notes: 1. See Table 16 for pins with internal pull-up resistors. 2. See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 16. 3.
Electrical and Thermal Characteristics 4.3 Power Characteristics Table 5 provides power consumption data for the MPC8245. Table 5. Power Consumption PCI Bus Clock/Memory Bus Clock/CPU Clock Frequency (MHz) Mode Unit Notes 2.2 W 1, 5 2.8 2.8 W 1, 2 2.2 2.4 2.4 W 1, 3 1.4 (1.3) 1.4 1.6 1.5 W 1, 4, 6 0.4 (0.4) 0.6 (0.6) 0.5 0.7 0.6 W 1, 4, 6 0.2 (0.4) 0.3 (0.3) 0.3 0.4 0.
Electrical and Thermal Characteristics 4.4 Thermal Characteristics Table 6 provides the package thermal characteristics for the MPC8245. For details, see Section 7.8, “Thermal Management.” Table 6. Thermal Characteristics Characteristic Symbol Value Unit Notes Junction-to-ambient natural convection (Single-layer board—1s) RθJA 16.1 °C/W 1, 2 Junction-to-ambient natural convection (Four-layer board—2s2p) RθJMA 12.
Electrical and Thermal Characteristics Table 7 provides the operating frequency information for the MPC8245 at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V. Table 7. Operating Frequency 1 266 MHz Characteristic 300 MHz 333 MHz 350 MHz 2, 3 VDD/AVDD/AV DD2 = 1.8/1.9/2.0 V ± 100 mV VDD/AVDD/AVDD2 = 2.0/2.
Electrical and Thermal Characteristics Table 8. Clock AC Timing Specifications (continued) At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V Num Characteristics and Conditions Min Max See Figure 8 through Figure 10 Unit Notes ns 6 16 DLL lock range for other modes 17 Frequency of operation (OSC_IN) 25 66 MHz 19 OSC_IN rise and fall times — 5 ns 20 OSC_IN duty cycle measured at 1.4 V 40 60 % 21 OSC_IN frequency stability — 100 ppm 7 Notes: 1.
Electrical and Thermal Characteristics Register settings that define each DLL mode are shown in Table 9. Table 9.
Electrical and Thermal Characteristics 30 27.5 Tclk SDRAM_SYNC_OUT Period (ns) 25 22.5 20 17.5 15 12.5 10 7.5 0 1 2 3 4 5 Tloop Propagation Delay Time (ns) Figure 7. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=0 and Normal Tap Delay MPC8245 Integrated Processor Hardware Specifications, Rev.
Electrical and Thermal Characteristics 30 27.5 Tclk SDRAM_SYNC_OUT Period (ns) 25 22.5 20 17.5 15 12.5 10 7.5 0 1 2 3 4 5 Tloop Propagation Delay Time (ns) Figure 8. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=1 and Normal Tap Delay MPC8245 Integrated Processor Hardware Specifications, Rev.
Electrical and Thermal Characteristics 30 27.5 Tclk SDRAM_SYNC_OUT Period (ns) 25 22.5 20 17.5 15 12.5 10 7.5 0 1 2 3 4 5 Tloop Propagation Delay Time (ns) Figure 9. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=0 and Max Tap Delay MPC8245 Integrated Processor Hardware Specifications, Rev.
Electrical and Thermal Characteristics 30 27.5 Tclk SDRAM_SYNC_OUT Period (ns) 25 22.5 20 17.5 15 12.5 10 7.5 0 1 2 3 4 5 Tloop Propagation Delay Time (ns) Figure 10. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=1 and Max Tap Delay 4.5.2 Input AC Timing Specifications Table 10 provides the input AC timing specifications at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V. MPC8245 Integrated Processor Hardware Specifications, Rev.
Electrical and Thermal Characteristics Table 10. Input AC Timing Specifications Num Characteristic Min Max Unit Notes 3.0 — ns 1, 3 ns 2, 3, 6 10a PCI input signals valid to PCI_SYNC_IN (input setup) 10b Memory input signals valid to sys_logic_clk (input setup) 10b0 Tap 0, register offset <0x77>, bits 5–4 = 0b00 2.6 — 10b1 Tap 1, register offset <0x77>, bits 5–4 = 0b01 1.9 — 10b2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default) 1.
Electrical and Thermal Characteristics Figure 11 and Figure 12 show the input/output timing diagrams referenced to SDRAM_SYNC_IN and PCI_SYNC_IN, respectively. PCI_SYNC_IN VM sys_logic_clk VM VM VM Tos SDRAM_SYNC_IN (after DLL locks) Shown in 2:1 Mode VM 10b-d 11a 13b 12b-d 2.0 V 2.0 V 0.8 V 0.8 V 14b Memory Inputs/Outputs Input Timing Output Timing Notes: VM = Midpoint voltage (1.4 V). 10b-d = Input signals valid timing. 11a = Input hold time of SDRAM_SYNC_IN to memory.
Electrical and Thermal Characteristics Figure 13 shows the input timing diagram for mode select signals. VM HRST_CPU/HRST_CTRL 10e 11b 2.0 V Mode Pins 0.8 V VM = Midpoint Voltage (1.4 V) Figure 13. Input Timing Diagram for Mode Select Signals 4.5.3 Output AC Timing Specification Table 11 provides the processor bus AC timing specifications for the MPC8245 at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V.
Electrical and Thermal Characteristics Table 11. Output AC Timing Specifications (continued) Num 14b Characteristic sys_logic_clk to output high impedance (for all others) Min Max Unit Notes — 4.0 ns 2 Notes: 1. All PCI signals are measured from GV DD/2 of the rising edge of PCI_SYNC_IN to 0.285 × OVDD or 0.615 × OVDD of the signal in question for 3.3 V PCI signaling levels. See Figure 12. 2. All memory and related interface output signal specifications are specified from the VM = 1.
Electrical and Thermal Characteristics Figure 15 provides the PCI_HOLD_DEL effect on output valid and hold times. OVDD/2 PCI_SYNC_IN OVDD /2 12a2, 7.0 ns for 33 MHz PCI PCI_HOLD_DEL = 10 13a2, 2.1 ns for 33-MHz PCI PCI_HOLD_DEL = 10 PCI Inputs/Outputs 33 MHz PCI 12a0, 6.0 ns for 66 MHz PCI PCI_HOLD_DEL = 00 13a0, 1 ns for 66-MHz PCI PCI_HOLD_DEL = 00 PCI Inputs/Outputs 66 MHz PCI As PCI_HOLD_DEL Values Decrease PCI Inputs and Outputs As PCI_HOLD_DEL Values Increase Note: Diagram not to scale.
Electrical and Thermal Characteristics Table 12. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 5%. Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 2 Input current each I/O pin (input voltage is between 0.1 × OVDD and 0.9 × OVDD(max) II –10 10 μA 3 Capacitance for each I/O pin CI — 10 pF Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2.
Electrical and Thermal Characteristics Table 13. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 12). Parameter Symbol 1 Min Max Unit Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 × OVDD — V Note: 1.
Electrical and Thermal Characteristics Figure 17 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2DVKH tI2CL tI2KHKL tI2CF tI2SXKL tI2CR SCL tI2SXKL tI2CH tI2DXKL,tI2OVKL S tI2SVKH tI2PVKH Sr P S Figure 17. I2C Bus AC Timing Diagram 4.7 PIC Serial Interrupt Mode AC Timing Specifications Table 14 provides the PIC serial interrupt mode AC timing specifications for the MPC8245 at recommended operating conditions (see Table 2) with GVDD = 3.3 V ± 5% and LVDD = 3.3 V ± 0.3 V.
Electrical and Thermal Characteristics sys_logic_clk VM VM VM 3 S_CLK 4 VM VM 5 4 S_FRAME VM VM S_RST Figure 18. PIC Serial Interrupt Mode Output Timing Diagram VM S_CLK 7 6 S_INT Figure 19. PIC Serial Interrupt Mode Input Timing Diagram 4.8 IEEE 1149.1 (JTAG) AC Timing Specifications Table 15 provides the JTAG AC timing specifications for the MPC8245 while in the JTAG operating mode at recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V.
Electrical and Thermal Characteristics Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) (continued) Num Characteristic Min Max Unit 11 TMS, TDI data hold time 15 — ns 12 TCK to TDO data valid 0 15 ns 13 TCK to TDO high impedance 0 15 ns Notes Notes: 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Nontest (other than TDI and TMS) signal input timing with respect to TCK. 3.
Package Description TCK 10 TDI, TMS 11 Input Data Valid 12 TDO Output Data Valid 13 TDO Figure 23. Test Access Port Timing Diagram 5 Package Description This section details package parameters, pin assignments, and dimensions. 5.1 Package Parameters The MPC8245 uses a 35 mm × 35 mm, cavity-up, 352-pin tape ball grid array (TBGA) package. The package parameters are as follows. Package Outline 35 mm × 35 mm Interconnects 352 Pitch 1.
Package Description 5.2 Pin Assignments and Package Dimensions Figure 24 shows the top surface, side profile, and pinout of the MPC8245, 352 TBGA package. –F– B CORNER –E– –T– 0.150 T A Top View Dot on top indicates corner of A1 pin on bottom 26 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 E G J L N R U W MAX A 34.8 35.2 B 34.8 35.2 C 1.45 1.65 D .60 .90 G 1.27 BASIC H .85 K L A C MIN .95 31.75 BASIC .50 .
Package Description 5.3 Pinout Listings Table 16 provides the pinout listing for the MPC8245, 352 TBGA package. Table 16.
Package Description Table 16.
Package Description Table 16.
Package Description Table 16.
Package Description Table 16. MPC8245 Pinout Listing (continued) Power Supply Output Driver Type Notes Power for core 1.8/2.0 V VDD — 22 D17 — — — 23 AV DD C17 Power for PLL (CPU core logic) 1.8/2.0 V AVDD — 22 AV DD2 AF24 Power for PLL (peripheral logic) 1.8/2.
Package Description Table 16. MPC8245 Pinout Listing (continued) Name DA[14:15] Pin Numbers F1 J2 Type Power Supply Output Driver Type Notes Output GVDD DRV_MEM_CTRL 2, 6 Notes: 1. Place a pull-up resistor of 120 Ω or less on the TEST0 pin. 2. Treat these pins as no connects (NC) unless debug address functionality is used. 3. This pin has an internal pull-up resistor that is enabled only in the reset state.
PLL Configurations 6 PLL Configurations The internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO) frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations are shown in Table 17 and Table 18. Table 17.
PLL Configurations Table 17. PLL Configurations (266- and 300-MHz Parts) (continued) 266-MHz Part 9 PCI Clock Input (PCI_ SYNC_IN) Range 1 (MHz) Periph Logic/ MemBus Clock Range (MHz) 300-MHz Part 9 CPU Clock Range (MHz) Multipliers PCI Clock Input (PCI_ SYNC_IN) Range 1 (MHz) Periph Logic/ MemBus Clock Range (MHz) CPU Clock Range (MHz) PCI-toMem (Mem VCO) Mem-toCPU (CPU VCO) 252,7 100 300 4 (2) 3 (2) 26 –42 52–84 182–294 2 (4) 3.5 (2) 273–305,7 68–75 272–300 2.5 (2) 4 (2) Ref. No.
PLL Configurations Table 17. PLL Configurations (266- and 300-MHz Parts) (continued) 266-MHz Part 9 Ref. No. PLL_CFG [0:4] 10,13 1F 111118 Periph Logic/ MemBus Clock Range (MHz) PCI Clock Input (PCI_ SYNC_IN) Range 1 (MHz) 300-MHz Part 9 CPU Clock Range (MHz) PCI Clock Input (PCI_ SYNC_IN) Range 1 (MHz) Not usable Periph Logic/ MemBus Clock Range (MHz) Multipliers CPU Clock Range (MHz) Not usable PCI-toMem (Mem VCO) Mem-toCPU (CPU VCO) Off Off Notes: 1.
PLL Configurations Table 18.
PLL Configurations Table 18.
System Design 7 System Design This section provides electrical and thermal design recommendations for successful application of the MPC8245. 7.1 PLL Power Supply Filtering The AVDD and AVDD2 power signals on the MPC8245 provide power to the peripheral logic/memory bus PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the AVDD and AVDD2 input signals should be filtered of any noise in the 500-kHz to 10-MHz resonant frequency range of the PLLs.
System Design 7.3 Connection Recommendations To ensure reliable operation, connect unused inputs to an appropriate signal level. Tie unused active-low inputs to OVDD. Connect unused active-high inputs tie to GND. All NC signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, GVDD, LVDD, and GND pins. The PCI_SYNC_OUT signal is to be routed halfway out to the PCI devices and returned to the PCI_SYNC_IN input of the MPC8245.
System Design The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP, QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks after the negation of HRST_CPU and HRST_CTRL.
System Design SRESET, TRIG_IN, and TRIG_OUT. The default state (logic 1) of SDMA1 selects the MPC8240 backward-compatible mode functionality, while a logic 0 state on the SDMA1 signal selects extended ROM functionality. In extended ROM mode, the TBEN, CHKSTOP_IN, SRESET, TRIG_IN, and TRIG_OUT functionalities are not available. The driver names and pin capability of the MPC8245 and the MPC8240 differ slightly.
System Design reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 26 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well.
System Design MPC8245 From Target Board Sources (if any) SRESET 5 SRESET 5 HRESET 7 13 11 HRST_CPU COP_HRESET 10 kΩ SRESET 5 10 kΩ 10 kΩ HRST_CTRL OVDD OVDD OVDD 10 kΩ 0Ω8 4 1 2 3 4 6 6 2 7 8 9 10 11 5 15 Key 14 4 12 KEY 13 No pin 15 16 COP Connector Physical Pin Out 8 9 1 3 TRST 7 COP_TRST VDD_SENSE 1 kΩ 10 kΩ OVDD OVDD 10 kΩ 3 COP Header 5 OVDD 10 kΩ CHKSTOP_IN 6 TMS TDO OVDD OVDD CHKSTOP_IN 6 TMS TDO TDI TCK 7 TDI TCK 2 NC 10 NC 12 NC QACK 1 16 Note: 1
System Design 7.8 Thermal Management This section provides thermal management information for the tape ball grid array (TBGA) package for air-cooled applications. Depending on the application environment and the operating frequency, heat sinks may be required to maintain junction temperature within specifications. Proper thermal control design primarily depends on the system-level design: the heat sink, airflow, and thermal interface material.
System Design Die Junction-to-Ambient Thermal Resistance (°C/W) 18 No heat sink and high thermal board-level loading of adjacent components No heat sink and low thermal board-level loading of adjacent components 16 Attached heat sink and high thermal board-level loading of adjacent components Attached heat sink and low thermal board-level loading of adjacent components 14 12 10 8 6 4 2 0 0.5 1 1.5 Airflow Velocity (m/s) 2 2.5 Figure 28.
System Design Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 603-635-5102 Selection of an appropriate heat sink depends on thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Other heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances and may or may not need airflow. 7.8.
System Design 7.8.2 Adhesives and Thermal Interface Materials A thermal interface material placed between the top of the package and the bottom of the heat sink minimizes thermal contact resistance. For applications that attach the heat sink by a spring clip mechanism, Figure 30 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.
System Design Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dow.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 7.8.
System Design RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the airflow around the device, the interface material, the mounting arrangement on the printed-circuit board, or the thermal dissipation on the printed-circuit board surrounding the device.
Document Revision History 8 Document Revision History Table 19 provides a revision history for this hardware specification. Table 19. Revision History Table Revision Date Substantive Change(s) 10 8/07 Section 3, Table 3, and Table 7—Changed format of recommended voltage supply values so that delta to the chosen nominal does not exceed ± 100 mV. Completely replaced Section 4.6 with compliant I2C specifications as with other related integrated processor devices.
Document Revision History Table 19. Revision History Table (continued) Revision Date Substantive Change(s) 5 — Section 4.1.2 — Added note 6 and related label for latching of the PLL_CFG signals. Section 4.1.3 — Updated specifications for the input high and input low voltages of PCI_SYNC_IN. Section 4.3 — Table 7, updated specifications for the voltage range of VDD for specific CPU frequencies. Section 4.3.
Document Revision History Table 19. Revision History Table (continued) Revision Date Substantive Change(s) 2 — Globally changed EPIC to PIC. Section 1.4.1.4—Note 5: Changed register reference from 0x72 to 0x73. Section 1.4.1.5—Table 5: Updated power dissipation numbers based on latest characterization data. Section 1.4.2—Table 6: Updated table to show more thermal specifications. Section 1.4.3—Table 7: Updated minimum memory bus value to 50 MHz. Section 1.4.3.
Document Revision History Table 19. Revision History Table (continued) Revision Date Substantive Change(s) 0.4 — Section 1.2—Changed Features list (format) to match with the features list of the MPC8245 Integrated Processor Reference Manual. Section 1.4.1.2—Updated Table 2 to include 1.8 ± 100mV numbers. Section 1.4.3—Changed Table 7 to include new part offerings of 333 and 350 MHz. Added rows to include VCO frequency ranges for all parts for both memory VCO and CPU VCO. Section 1.4.1.
Document Revision History Table 19. Revision History Table (continued) Revision Date Substantive Change(s) 0.2 — Changed core supply voltage to 2.0 ± 100 mV in Section 1.3. (Supply voltage of 1.8 ± 100 mV is no longer recommended.) Changed rows 2, 5, and 6 of Table 2 to 2.0 ± 100 mV in the “Recommended Value” column. Changed the power consumption numbers in Table 5 to reflect the power values for VDD = 2.0 V. (Notes 2, 3, 4, and 5 of the table were also updated to reflect the new value of VDD.
Document Revision History Table 19. Revision History Table (continued) Revision Date Substantive Change(s) 0.1 — Made VDD/AVDD/AVDD2 = 1.8 V ± 100 mV information for 133-MHz memory interface operation to Section 1.3, Table 2, Table 5, Table 9, Table 17, and Section 1.7.2. Pin D17, formerly LAVDD (supply voltage for DLL), is a NC on the MPC8245 since the DLL voltage is supplied internally. Eliminated all references to LAVDD; updated Section 1.7.1.
Ordering Information 9 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 9.1, “Part Numbers Fully Addressed by This Document.” Section 9.2, “Part Numbers Not Fully Addressed by This Document,” lists the part numbers that do not fully conform to the specifications of this document. These special part numbers require an additional document called a hardware specifications addendum. 9.
Ordering Information 9.2 Part Numbers Not Fully Addressed by This Document Parts with application modifiers or revision levels not fully addressed in this specification document are described in separate part number specifications that supplement and supersede this document. Table 21 shows the part numbers addressed by the MPC8245TXXnnnx series. The revision level can be determined by reading the Revision ID register at address offset 0x08. Table 21.
Ordering Information 9.3 Part Marking Parts are marked as the example shown in Figure 31. MPC8245LXXnnnx ATWLYYWW CCCCC MMMMM YWWLAZ Notes: MMMMM is the 5-digit mask number. ATWLYYWW is test traceability code. YWWLAZ is the assembly traceability code. CCCCC is the country code. Figure 31. Part Marking for TBGA Device MPC8245 Integrated Processor Hardware Specifications, Rev.
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