Datasheet

MPC8245 Integrated Processor Hardware Specifications, Rev. 10
14 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 7 provides the operating frequency information for the MPC8245 at recommended operating
conditions (see Table 2) with LV
DD
= 3.3 V ± 0.3 V.
4.5.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications at recommended operating conditions, as defined in
Section 4.5.2, “Input AC Timing Specifications.” These specifications are for the default driver strengths
indicated in Table 4.
Table 7. Operating Frequency
1
Characteristic
2, 3
266 MHz 300 MHz 333 MHz 350 MHz
Unit
V
DD
/AV
DD
/AV
DD
2 = 1.8/1.9/2.0 V
± 100 mV
V
DD
/AV
DD
/AV
DD
2 = 2.0/2.1 V
± 100 mV
Processor frequency (CPU) 100–266 100–300 100–333 100–350 MHz
Memory bus frequency 50–133 50–100
4
50–133 50–100
4
MHz
PCI input frequency 25–66 MHz
Notes:
1. For details, refer to the hardware specifications addendum MPC8245ECSO2AD.
2. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral
logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Section 6, “PLL Configurations,” for valid PLL_CFG[0:4] settings
and PCI_SYNC_IN frequencies.
3. See Table 17 and Table 18 for details on VCO limitations for memory and CPU VCO frequencies of various PLL
configurations.
4. No available PLL_CFG[0:4] settings support 133-MHz memory interface operation at 300- and 350-MHz CPU operation,
since the multipliers do not allow a 300:133 and 350:133 ratio relation. However, running these parts at slower processor
speeds may produce ratios that run above 100 MHz. See Table 17 for the PLL settings.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (see Table 2) with LV
DD
= 3.3 V ± 0.3 V
Num Characteristics and Conditions Min Max Unit Notes
1 Frequency of operation (PCI_SYNC_IN) 25 66 MHz
2, 3 PCI_SYNC_IN rise and fall times — 2.0 ns 1
4 PCI_SYNC_IN duty cycle measured at 1.4 V 40 60 %
5a PCI_SYNC_IN pulse width high measured at 1.4 V 6 9 ns 2
5b PCI_SYNC_IN pulse width low measured at 1.4 V 6 9 ns 2
7 PCI_SYNC_IN jitter — 200 ps
8a PCI_CLK[0:4] skew (pin-to-pin) — 250 ps
8b SDRAM_CLK[0:3] skew (pin-to-pin) — 190 ps 3
10 Internal PLL relock time — 100 µs 2, 4, 5
15 DLL lock range with DLL_EXTEND = 0 (disabled)
and normal tap delay; (default DLL mode)
See Figure 7 ns 6