Datasheet

MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 15
Electrical and Thermal Characteristics
Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled number items listed in
Table 8.
Figure 6. PCI_SYNC_IN Input Clock Timing Diagram
Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation. These
graphs define the areas of DLL locking for various modes. The gray areas show where the DLL locks.
16 DLL lock range for other modes See Figure 8 through Figure 10 ns 6
17 Frequency of operation (OSC_IN) 25 66 MHz
19 OSC_IN rise and fall times — 5 ns 7
20 OSC_IN duty cycle measured at 1.4 V 40 60 %
21 OSC_IN frequency stability — 100 ppm
Notes:
1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
2. Specification value at maximum frequency of operation.
3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew
added to the clocking signals from the variable length DLL synchronization feedback loop, that is, the amount of variance
between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin-to-pin skew between
SDRAM_CLKs can be measured, the relationship between the internal sys_logic_clk and the external SDRAM_SYNC_IN
cannot be measured and is guaranteed by design.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable
V
DD
and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been
disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU
/HRST_CTRL must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see Figure 7 through Figure 10). T
clk
is the period
of one SDRAM_SYNC_OUT clock cycle in ns. T
loop
is the propagation delay of the DLL synchronization feedback loop (PC
board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner)
corresponds to approximately 1 ns of delay. For details about how Figure 7 through Figure 10 may be used refer to the
Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines,
for details on MPC8245
memory clock design.
7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are
not tested.
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions (see Table 2) with LV
DD
= 3.3 V ± 0.3 V
Num Characteristics and Conditions Min Max Unit Notes
5a
5b
VM
VM = Midpoint Voltage (1.4 V)
2 3
1
PCI_SYNC_IN
VM VM