Datasheet

MPC8245 Integrated Processor Hardware Specifications, Rev. 10
2 Freescale Semiconductor
Overview
Figure 1. MPC8245 Block Diagram
Peripheral Logic Bus
Instruction Unit
System
Integer Load/Store
Floating-
Data Instruction
16-Kbyte 16-Kbyte
Processor Core Block
Processor
PLL
(64-Bit) Two-Instruction Fetch
(64-Bit) Two-Instruction Dispatch
64-Bit
Branch
Processing
Unit
(BPU)
MPC8245
Register
Unit
(SRU)
Unit
(IU)
Unit
(LSU)
Point
Unit
(FPU)
Data
Cache
Instruction
Cache
MMUMMU
Additional Features:
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
Address
Translator
DLL
Fanout
Buffers
PCI
Arbiter
Message
Unit
(with I
2
O)
I
2
C
Controller
DMA
Controller
Interrupt
Controller/
PIC
Timers
PCI Bus
Interface Unit
Memory
Controller
Data Path
ECC Controller
Central
Control
Unit
32-Bit
OSC_IN
Five
Request/Grant Pairs
I
2
C
5 IRQs/
Peripheral Logic Block
Peripheral Logic
PLL
PCI Bus
Data (64-Bit)
Address
Data Bus
(32- or 64-Bit)
Memory/ROM/
PortX Control/Address
PCI Interface
Clocks
16 Serial
Interrupts
Configuration
Registers
(32-Bit)
with 8-Bit Parity
or ECC
PCI_SYNC_IN
SDRAM_SYNC_IN
Watchpoint
Facility
DUART
Performance
Monitor
SDRAM Clocks