Datasheet

MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 21
Electrical and Thermal Characteristics
Table 10. Input AC Timing Specifications
Num Characteristic Min Max Unit Notes
10a PCI input signals valid to PCI_SYNC_IN (input setup) 3.0 — ns 1, 3
10b Memory input signals valid to sys_logic_clk (input setup)
10b0 Tap 0, register offset <0x77>, bits 5–4 = 0b00 2.6 — ns 2, 3, 6
10b1 Tap 1, register offset <0x77>, bits 5–4 = 0b01 1.9 —
10b2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default) 1.2 —
10b3 Tap 3, register offset <0x77>, bits 5–4 = 0b11 0.5 —
10c PIC, misc. debug input signals valid to sys_logic_clk
(input setup)
3.0 — ns 2, 3
10d I
2
C input signals valid to sys_logic_clk (input setup) 3.0 — ns 2, 3
10e Mode select inputs valid to HRST_CPU
/HRST_CTRL (input setup) 9 × t
CLK
— ns 2, 3–5
11 T
os
—SDRAM_SYNC_IN to sys_logic_clk offset time 0.4 1.0 ns 7
11a sys_logic_clk to memory signal inputs invalid (input hold)
11a0 Tap 0, register offset <0x77>, bits 5–4 = 0b00 0 — ns 2, 3, 6
11a1 Tap 1, register offset <0x77>, bits 5–4 = 0b01 0.7 —
11a2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default) 1.4 —
11a3 Tap 3, register offset <0x77>, bits 5–4 = 0b11 2.1 —
11b HRST_CPU
/HRST_CTRL to mode select inputs invalid (input hold) 0 — ns 2, 3, 5
11c PCI_SYNC_IN to Inputs invalid (input hold) 1.0 — ns 1, 2, 3
Notes:
1. All PCI signals are measured from OV
DD
/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV
DD
of the signal in question for
3.3-V PCI signaling levels. See Figure 12.
2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in
question to the VM = 1.4 V of the rising edge of the memory bus clock, sys_logic_clk. sys_logic_clk is the same as
PCI_SYNC_IN in 1:1 mode but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every
rising and falling edge of PCI_SYNC_IN). See Figure 11.
3. Input timings are measured at the pin.
4. t
CLK
is the time of one SDRAM_SYNC_IN clock cycle.
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the
VM = 1.4 V of the rising edge of the HRST_CPU
/HRST_CTRL signal. See Figure 13.
6. The memory interface input setup and hold times are programmable to four possible combinations by programming bits 5–4
of register offset <0x77> to select the desired input setup and hold times.
7. T
os
represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay present
on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM clocks become
offset by the delay amount. To maintain phase-alignment of the memory clocks with respect to sys_logic_clk, the feedback
trace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened to accommodate this range. The feedback
trace length is relative to the SDRAM clock output trace lengths. We recommend that the length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN be shortened by 0.7 ns because that is the midpoint of the range of T
os
and allows the impact from the
range of T
os
to be reduced. Additional analyses of trace lengths and SDRAM loading must be performed to optimize timing.
For details on trace measurements and the problem of T
os
, refer to the Freescale application note AN2164,
MPC8245/MPC8241 Memory Clock Design Guidelines.