Datasheet

MPC8245 Integrated Processor Hardware Specifications, Rev. 10
22 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11 and Figure 12 show the input/output timing diagrams referenced to SDRAM_SYNC_IN and
PCI_SYNC_IN, respectively.
Figure 11. Input/Output Timing Diagram Referenced to SDRAM_SYNC_IN
Figure 12. Input/Output Timing Diagram Referenced to PCI_SYNC_IN
11a
VM = Midpoint voltage (1.4 V).
Memory
10b-d
Inputs/Outputs
13b
14b
VM
VM
SDRAM_SYNC_IN
Input Timing Output Timing
12b-d
2.0 V
0.8 V
0.8 V
2.0 V
T
os
11a = Input hold time of SDRAM_SYNC_IN to memory.
12b-d = sys_logic_clk to output valid timing.
13b = Output hold time for non-PCI signals.
14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals.
T
os
= Offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal
sys_logic_clk
VM
PCI_SYNC_IN
VM
VM
is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to appear
before sys_logic_clk once the DLL locks.
(after DLL locks)
Shown in 2:1 Mode
Notes:
10b-d = Input signals valid timing.
OV
DD
÷ 2
10a
11c
PCI_SYNC_IN
PCI
12a
13a
14a
OV
DD
÷ 2
OV
DD
÷ 2
0.4 × OV
DD
0.615 × OV
DD
0.285 × OV
DD
Input Timing Output Timing
Inputs/Outputs