Datasheet

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor 23

Electrical and Thermal Characteristics

Figure 13 shows the input timing diagram for mode select signals.

Figure 13. Input Timing Diagram for Mode Select Signals

4.5.3 Output AC Timing Specification

Table 11 provides the processor bus AC timing specifications for the MPC8245 at recommended operating

conditions (see Table 2) with LV

= 3.3 V ± 0.3 V. See Figure 11 for the input/output timing diagram

referenced to sys_logic_clk. All output timings assume a purely resistive 50-Ω load (see Figure 14 for the

AC test load for the MPC8245). Output timings are measured at the pin; time-of-flight delays must be

added for trace lengths, vias, and connectors in the system. These specifications are for the default driver

strengths indicated in Table 4.

Table 11. Output AC Timing Specifications

Num Characteristic Min Max Unit Notes

12a PCI_SYNC_IN to output valid, see Figure 15

12a0 Tap 0, PCI_HOLD_DEL=00, [MCP

,CKE] = 11, 66 MHz PCI (default) — 6.0 ns 1, 3

12a1 Tap 1, PCI_HOLD_DEL=01, [MCP

,CKE] = 10 — 6.5

12a2 Tap 2, PCI_HOLD_DEL=10, [MCP

,CKE] = 01, 33 MHz PCI — 7.0

12a3 Tap 3, PCI_HOLD_DEL=11, [MCP

,CKE] = 00 — 7.5

12b sys_logic_clk to output valid (memory control, address, and data signals) — 4.0 ns 2

12c sys_logic_clk to output valid (for all others) — 7.0 ns 2

12d sys_logic_clk to output valid (for I

C) — 5.0 ns 2

12e sys_logic_clk to output valid (ROM/Flash/PortX) — 6.0 ns 2

13a Output hold (PCI), see Figure 15

13a0 Tap 0, PCI_HOLD_DEL=00, [MCP

,CKE] = 11, 66-MHz PCI (default) 2.0 — ns 1, 3, 4

13a1 Tap 1, PCI_HOLD_DEL=01, [MCP

,CKE] = 10 2.5 —

13a2 Tap 2, PCI_HOLD_DEL=10, [MCP

,CKE] = 01, 33-MHz PCI 3.0 —

13a3 Tap 3, PCI_HOLD_DEL=11, [MCP

,CKE] = 00 3.5 —

13b Output hold (all others) 1.0 — ns 2

14a PCI_SYNC_IN to output high impedance (for PCI) — 14.0 ns 1, 3

VM = Midpoint Voltage (1.4 V)

11b

Mode Pins

10e

HRST_CPU/HRST_CTRL

2.0 V

0.8 V