Datasheet
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 7
Electrical and Thermal Characteristics
PLL supply voltage—peripheral logic AV
DD
2 1.8/1.9/2.0 V ± V 4, 7, 12
2.0/2.1 V ± V 5, 7, 12
PCI reference LV
DD
5.0 ± 5% V 2, 10, 11
3.3 ± 0.3 V 3, 10, 11
Input voltage PCI inputs V
in
0 to 3.6 or 5.75 V 2, 3
All other inputs 0 to 3.6 V 6
Die-junction temperature T
j
0 to 105 °C
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
2. PCI pins are designed to withstand LV
DD
+ 5% V DC when LV
DD
is connected to a 5.0-V DC power supply.
3. PCI pins are designed to withstand LV
DD
+ 0.5 V DC when LV
DD
is connected to a 3.3-V DC power supply.
4. The voltage supply value of 1.8/1.9/2.0 V ± 100 mV applies to parts marked as having a maximum CPU speed of 266 and
300 MHz. See Table 7. For each chosen nominal value (1.8/1.9/2.0 V) the supply voltage should not exceed ± 100 mV of
the nominal value.
5. The voltage supply value of 2.0/2.1 V ± 100 m V applies to parts marked as having a maximum CPU speed of 333 and 350
MHz. See Table 7. For each chosen nominal value (2.0/2.1 V) the supply voltage should not exceed ± 100 mV of the nominal
value.
Cautions:
6. Input voltage (V
in
) must not be greater than the supply voltage (V
DD
/AV
DD
/AV
DD
2) by more than 2.5 V at all times, including
during power-on reset. Input voltage (V
in
) must not be greater than GV
DD
/OV
DD
by more than 0.6 V at all times, including
during power-on reset.
7. OV
DD
must not exceed V
DD
/AV
DD
/AV
DD
2 by more than 1.8 V at any time, including during power-on reset. This limit may
be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
8. V
DD
/AV
DD
/AV
DD
2 must not exceed OV
DD
by more than 0.6 V at any time, including during power-on reset. This limit may
be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
9. GV
DD
must not exceed V
DD
/AV
DD
/AV
DD
2 by more than 1.8 V at any time, including during power-on reset. This limit may
be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
10.LV
DD
must not exceed V
DD
/AV
DD
/AV
DD
2 by more than 5.4 V at any time, including during power-on reset. This limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
11. LV
DD
must not exceed OV
DD
by more than 3.0 V at any time, including during power-on reset. This limit may be exceeded
for a maximum of 20 ms during power-on reset and power-down sequences.
12.This voltage is the input to the filter discussed in Section 7.1, “PLL Power Supply Filtering,” and not necessarily the voltage
at the AV
DD
pin, which may be reduced from V
DD
by the filter.
Table 2. Recommended Operating Conditions
1
(continued)
Characteristic Symbol
Recommended
Value
Unit Notes