Freescale Semiconductor Technical Data Document Number: MPC8260AEC Rev. 2.0, 06/2009 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for .25μm (HiP4) devices in the PowerQUICC II™ MPC8260 communications processor family. These devices include the MPC8260, the MPC8255, the MPC8264, the MPC8265, and the MPC8266.
Features Figure 1 shows the block diagram for the MPC8266, the HiP4 superset device. Shaded portions indicate functionality that is not available on all devices; refer to the notes.
Features • • • • • • • — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz without inlining and 1.
Features • • — 32-bit address decodes with programmable bank size — Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine — Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) — Dedicated interface logic for SDRAM CPU core can be disabled and the device can be used in slave mode to an external core Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible suppor
Features — — — — — – Transparent – UART (low-speed operation) One serial peripheral interface identical to the MPC860 SPI One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) – Microwire compatible – Multiple-master, single-master, and slave modes Up to eight TDM interfaces (four on the MPC8255) – Supports two groups of four TDM channels for a total of eight TDMs – 2,048 bytes of SI RAM – Bit or byte resolution – Independent transmit and receive routing, frame synchroni
Features • - Coset removing (programmable by the user) - Filtering idle/unassigned cells (programmable by the user) - Performing HEC error detection and single bit error correction (programmable by user) - Generating loss of cell delineation status/interrupt (LOC/LCD) — Operates with FCC2 (UTOPIA 8) — Provides serial loop back mode — Cell echo mode is provided — Supports both FCC transmit modes – External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.
Electrical and Thermal Characteristics — Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) — Support for 66 MHz, 3.3 V specification — 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port — Makes use of the local bus signals, so there is no need for additional pins 2 Electrical and Thermal Characteristics This section provides AC and DC electrical specifications and thermal characteristics for the MPC826xA. 2.
Electrical and Thermal Characteristics Table 2 lists recommended operational voltage conditions. Table 2. Recommended Operating Conditions1 Rating Symbol 2 3 4 5 Unit Core supply voltage VDD 1.7 – 1.92 1.7–2.13 1.9 –2.24 V PLL supply voltage VCCSYN 1.7 – 1.92 1.7–2.13 1.9–2.24 V I/O supply voltage VDDH 3.135 – 3.465 V VIN GND (–0.3) – 3.
Electrical and Thermal Characteristics Table 3 shows DC electrical characteristics. Table 3. DC Electrical Characteristics1 Characteristic Symbol Min Max Unit Input high voltage, all inputs except CLKIN VIH 2.0 3.465 V Input low voltage VIL GND 0.8 V VIHC 2.4 3.465 V VILC GND 0.4 V CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = VDDH 2 IIN — 10 µA Hi-Z (off state) leakage current, VIN = VDDH2 Signal low input current, VIL = 0.
Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics1 (continued) Characteristic IOL = 7.
Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics1 (continued) Characteristic IOL = 5.
Electrical and Thermal Characteristics 2 The leakage current is measured for nominal VDD, VCCSYN, and VDD. MPC8265 and MPC8266 only. 3 2.2 Thermal Characteristics Table 4 describes thermal characteristics. Table 4. Thermal Characteristics for 480 TBGA Package Characteristics Symbol Value Unit Air Flow 131 Junction to ambient θJA 101 NC2 1 m/s °C/W 113 NC 83 1 m/s Junction to board4 θJB 4 °C/W — Junction to case5 θJC 1.
Electrical and Thermal Characteristics where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. 2.3.1 Layout Practices Each VCC pin should be provided with a low-impedance path to the board’s power supply. Each ground pin should likewise be provided with a low-impedance path to ground.
Electrical and Thermal Characteristics 2.4 AC Electrical Characteristics The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for the 66 MHz MPC826xA device. Note that AC timings are based on a 50-pf load. Typical output buffer impedances are shown in Table 6. Table 6. Output Buffer Impedances1 Output Buffers Typical Impedance (Ω) 60x bus 40 Local bus 40 Memory controller 40 Parallel I/O 46 PCI 25 1 These are typical values at 65° C.
Electrical and Thermal Characteristics Table 8 lists CPM input characteristics. Table 8. AC Characteristics for CPM Inputs1 Spec Number Setup (ns) Hold (ns) Characteristic 1 Max Min 66 MHz 83 MHz 66 MHz 83 MHz sp16a sp17a FCC inputs—internal clock (NMSI) 10 8 0 0 sp16b sp17b FCC inputs—external clock (NMSI) 3 2.
Electrical and Thermal Characteristics Figure 4 shows the FCC internal clock. BRG_OUT sp17a sp16a FCC input signals sp36a/sp37a FCC output signals Note: When GFMR[TCI] = 0 sp36a/sp37a FCC output signals Note: When GFMR[TCI] = 1 Figure 4. FCC Internal Clock Diagram Figure 5 shows the SCC/SMC/SPI/I2C external clock. Serial CLKin sp18b sp19b SCC/SMC/SPI/I2C input signals (See note.) sp38b/sp39b SCC/SMC/SPI/I2C output signals (See note.
Electrical and Thermal Characteristics Figure 6 shows the SCC/SMC/SPI/I2C internal clock. BRG_OUT sp19a sp18a SCC/SMC/SPI/I2C input signals (See note.) sp38a/sp39a SCC/SMC/SPI/I2C output signals (See note.) Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4.
Electrical and Thermal Characteristics Figure 8 shows PIO, timer, and DMA signals. Sys clk sp23 sp22 PIO/IDMA/TIMER[TGATE assertion] input signals (See note) sp23 sp22 TIMER input signal [TGATE deassertion] (See note) sp42/sp43 IDMA output signals sp42/sp43 sp42a/sp43a TIMER(sp42/43)/ PIO(sp42a/sp43a) output signals Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge. Figure 8. PIO, Timer, and DMA Signal Diagram Table 10 lists SIU input characteristics.
Electrical and Thermal Characteristics Table 10 lists SIU output characteristics. Table 10. AC Characteristics for SIU Outputs1 Spec Number Max Delay (ns) Min Delay (ns) Characteristic 1 Max Min 66 MHz 83 MHz 66 MHz 83 MHz sp31 sp30 PSDVAL/TEA/TA 7 6 0.5 0.5 sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT 8 6.5 0.5 0.5 sp33a sp30 Data bus 6.5 6.5 0.5 0.5 sp33b sp30 DP 8 7 0.5 0.5 sp34 sp30 Memory controller signals/ALE 6 5 0.5 0.5 sp35 sp30 All other signals 6 5.5 0.
Electrical and Thermal Characteristics Figure 9 shows the interaction of several bus signals. CLKin sp11 sp10 AACK/ARTRY/TA/TS/TEA/ DBG/BG/BR input signals sp12 sp10 sp15 sp10 DATA bus normal mode input signal All other input signals sp30 sp31 PSDVAL/TEA/TA output signals sp32 sp30 sp33a sp30 sp35 sp30 ADD/ADD_atr/BADDR/CI/ GBL/WT output signals DATA bus output signals All other output signals Figure 9.
Electrical and Thermal Characteristics Figure 11 shows signal behavior in MEMC mode. CLKin V_CLK sp34/sp30 Memory controller signals Figure 11. MEMC Mode Diagram NOTE Generally, all MPC826xA bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin.
Electrical and Thermal Characteristics Table 12 lists the JTAG timings. Table 12.
Clock Configuration Modes 3 Clock Configuration Modes To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the MODCK[1–3] pins are sampled while HRESET is asserted. Table 13 lists the eight basic configuration modes. Table 14 lists the other modes that are available by using the configuration pin (RSTCONF) and driving four bits from hardware configuration word on the data bus.
Clock Configuration Modes Table 14.
Clock Configuration Modes Table 14. Clock Configuration Modes1 (continued) MODCK_H–MODCK[1–3] Input Clock Frequency2,3 CPM Multiplication Factor2 0100_111 Core Multiplication CPM Core Factor2 Frequency2 Frequency2 Reserved 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 66 MHz 2 133 MHz 2 133 MHz 0101_110 66 MHz 2 133 MHz 2.5 166 MHz 0101_111 66 MHz 2 133 MHz 3 200 MHz 0110_000 66 MHz 2 133 MHz 3.
Clock Configuration Modes Table 14. Clock Configuration Modes1 (continued) MODCK_H–MODCK[1–3] Input Clock Frequency2,3 CPM Multiplication Factor2 Core Multiplication CPM Core Factor2 Frequency2 Frequency2 1000_001 66 MHz 3.5 233 MHz 3 200 MHz 1000_010 66 MHz 3.5 233 MHz 3.5 233 MHz 1000_011 66 MHz 3.5 233 MHz 4 266 MHz 1000_100 66 MHz 3.5 233 MHz 4.5 300 MHz 1 Because of speed dependencies, not all of the possible configurations in Table 14 are applicable.
Clock Configuration Modes 3.2.1 PCI Host Mode The frequencies listed in Table 16 and Table 17 are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. I Table 16.
Clock Configuration Modes Table 17.
Clock Configuration Modes Table 17. Clock Configuration Modes in PCI Host Mode (continued) Core CPM Core PCI Division CPM PCI Multiplication Multiplication Frequency Factor2 Frequency Frequency2 Factor Factor MODCK_H – MODCK[1–3] Input Clock Frequency1 (Bus) 1001_010 66 MHz 3.5 233 MHz 3.5 233 MHz 4/8 58/29 MHz 1001_011 66 MHz 3.5 233 MHz 4 266 MHz 4/8 58/29 MHz 1001_100 66 MHz 3.5 233 MHz 4.
Clock Configuration Modes Table 18. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000) (continued) Core Input Clock CPM Core CPM Bus Division 60x Bus Multiplication MODCK[1–3]1 Frequency Multiplication 3 Frequency Frequency Factor Frequency4 Factor (PCI)2 Factor2 100 66/33 MHz 3/6 200 MHz 3 240 MHz 2.5 80 MHz 101 66/33 MHz 3/6 200 MHz 3.5 280 MHz 2.5 80 MHz 110 66/33 MHz 4/8 266 MHz 3.5 300 MHz 3 88 MHz 111 66/33 MHz 4/8 266 MHz 3 300 MHz 2.
Clock Configuration Modes Table 19. Clock Configuration Modes in PCI Agent Mode (continued) Input Clock Core CPM Core MODCK_H – CPM Bus Division 60x Bus Frequency Multiplication Multiplication Frequency3 MODCK[1–3] Frequency Factor Frequency4 1,2 1 (PCI) Factor Factor 0100_100 66/33 MHz 3/6 200 MHz 4.5 300 MHz 3 66 MHz 0101_0005 33 MHz 5 166 MHz 2.5 166 MHz 2.5 66 MHz 5 0101_001 33 MHz 5 166 MHz 3 200 MHz 2.5 66 MHz 0101_0105 33 MHz 5 166 MHz 3.5 233 MHz 2.
Clock Configuration Modes Table 19. Clock Configuration Modes in PCI Agent Mode (continued) Input Clock Core CPM Core MODCK_H – CPM Bus Division 60x Bus Frequency Multiplication Multiplication Frequency3 MODCK[1–3] Frequency Factor Frequency4 1,2 1 (PCI) Factor Factor 1 2 3 4 5 1010_001 66/33 MHz 4/8 266 MHz 3 266 MHz 3 88 MHz 1010_010 66/33 MHz 4/8 266 MHz 3.5 300 MHz 3 88 MHz 1010_011 66/33 MHz 4/8 266 MHz 4 350 MHz 3 88 MHz 1010_100 66/33 MHz 4/8 266 MHz 4.
Pinout 4 Pinout This section provides the pin assignments and pinout list for the MPC826xA. 4.1 Pin Assignments Figure 13 shows the pinout of the MPC826xA’s 480 TBGA package as viewed from the top surface.
Pinout Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view. View Copper Heat Spreader (Oxidized for Insulation) Etched Cavity Die Attach Polymide Tape Pressure Sensitive Adhesive Die Soldermask Glob-Top Filled Area Glob-Top Dam Copper Traces 1.27 mm Pitch Wire Bonds Figure 14. Side View of the TBGA Package Table 21 shows the pinout list of the MPC826xA. Table 20 defines conventions and acronyms used in Table 21.
Pinout Table 21. Pinout List (continued) Pin Name Ball A8 J1 A9 K4 A10 K3 A11 K2 A12 K1 A13 L5 A14 L4 A15 L3 A16 L2 A17 L1 A18 M5 A19 N5 A20 N4 A21 N3 A22 N2 A23 N1 A24 P4 A25 P3 A26 P2 A27 P1 A28 R1 A29 R3 A30 R5 A31 R4 TT0 F1 TT1 G4 TT2 G3 TT3 G2 TT4 F2 TBST D3 TSIZ0 C1 TSIZ1 E4 TSIZ2 D2 TSIZ3 F5 AACK F3 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.
Pinout Table 21. Pinout List (continued) Pin Name Ball ARTRY E1 DBG V1 DBB/IRQ3 V2 D0 B20 D1 A18 D2 A16 D3 A13 D4 E12 D5 D9 D6 A6 D7 B5 D8 A20 D9 E17 D10 B15 D11 B13 D12 A11 D13 E9 D14 B7 D15 B4 D16 D19 D17 D17 D18 D15 D19 C13 D20 B11 D21 A8 D22 A5 D23 C5 D24 C19 D25 C17 D26 C15 D27 D13 D28 C11 D29 B8 D30 A4 D31 E6 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.
Pinout Table 21.
Pinout Table 21.
Pinout Table 21.
Pinout Table 21.
Pinout Table 21.
Pinout Table 21.
Pinout Table 21.
Pinout Table 21.
Pinout Table 21.
Package Description 3 On PCI devices (MPC8265 and MPC8266) this pin should be used as CLKIN2. On non-PCI devices (MPC8260A and MPC8264) this is a spare pin that must be pulled down or left floating. 4 Must be pulled down or left floating. 5 On PCI devices (MPC8265 and MPC8266) this pin should be asserted if the PCI function is desired or pulled up or left floating if PCI is not desired. On non-PCI devices (MPC8260A and MPC8264) this is a spare pin that must be pulled up or left floating.
Package Description 5.2 Mechanical Dimensions Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package. Notes: 1. Dimensions and Tolerancing per ASME Y14.5M-1994. 2. Dimensions in millimeters. 3. Dimension b is measured at the maximum solder ball diameter, parallel to primary data A. Millimeters Dim Min Max A 1.45 1.65 A1 0.60 0.70 A2 0.85 0.95 A3 0.25 — b 0.65 0.85 D 37.50 BSC D1 35.56 REF e 1.27 BSC E 37.50 BSC E1 35.
Ordering Information 6 Ordering Information Figure 16 provides an example of the Freescale part numbering nomenclature for the MPC826xA. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only.
Document Revision History Table 23. Document Revision History (continued) Revision Date Substantive Changes 0.9 8/2003 • Note: In revision 0.3, sp30 (Table 10) was changed. This change was not previously recorded in this “Document Revision History” Table. • Removal of “HiP4 PowerQUICC II Documentation” table. These supplemental specifications have been replaced by revision 1 of the MPC8260 PowerQUICC II™ Family Reference Manual.
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.
