Datasheet

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
Freescale Semiconductor 19
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
Table 10. AC Characteristics for SIU Outputs
1
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
Spec Number
Characteristic
Max Delay (ns) Min Delay (ns)
Max Min 66 MHz 83 MHz 66 MHz 83 MHz
sp31 sp30 PSDVAL
/TEA/TA 760.50.5
sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT 8 6.5 0.5 0.5
sp33a sp30 Data bus 6.5 6.5 0.5 0.5
sp33b sp30 DP 8 7 0.5 0.5
sp34 sp30 Memory controller signals/ALE 6 5 0.5 0.5
sp35 sp30 All other signals 6 5.5 0.5 0.5