Datasheet

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
2 Freescale Semiconductor
Features
Figure 1 shows the block diagram for the MPC8266, the HiP4 superset device. Shaded portions indicate
functionality that is not available on all devices; refer to the notes.
Figure 1. MPC8266 Block Diagram
1 Features
The major features of the MPC826xA family are as follows:
• Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–300 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
16 Kbytes
G2 Core
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
32 Kbytes
32-bit RISC Microcontroller
and Program ROM
Serial
DMAs
4 Virtual
IDMAs
60x-to-PCI
Bridge
2,3
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
Local Bus
32 bits, up to 83 MHz
PCI Bus
2,3
32 bits, up to 66 MHz
or
MCC1
4
MCC2 FCC1 FCC2 FCC3
4
SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI
I
2
C
Serial Interface
3 MII 2 UTOPIA
PortsPorts
6
60x Bus
Microcode
IMA
1,3
Dual-Port RAM
Interrupt
Controller
Time Slot Assigner
TC Layer Hardware
1,3
8 TDM Ports
5
Non-Multiplexed
I/O
60x-to-Local
Bus Interface Unit
Notes:
1
MPC8264
2
MPC8265
3
MPC8266
4
Not on MPC8255
5
4 TDM ports on the MPC8255
6
2 MII ports on the MPC8255