Datasheet

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
22 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 12 lists the JTAG timings.
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
Table 12. JTAG Timings
1
Parameter Symbol
2
Min Max Unit Notes
JTAG external clock frequency of operation f
JTG
025MHz—
JTAG external clock cycle time t
JTG
40 — ns —
JTAG external clock pulse width measured at 1.4V t
JTKHKL
20 — ns —
JTAG external clock rise and fall times t
JTGR
and
t
JTGF
05ns6
TRST assert time t
TRST
25 — ns 3, 6
Input setup times
Boundary-scan data
TMS, TDI
t
JTDVKH
t
JTIVKH
4
4
—
—
ns
ns
4, 7
4, 7
Input hold times
Boundary-scan data
TMS, TDI
t
JTDXKH
t
JTIXKH
10
10
—
—
ns
ns
4, 7
4, 7
Output valid times
Boundary-scan data
TDO
t
JTKLDV
t
JTKLOV
—
—
25
25
ns
ns
5, 7
5. 7
Output hold times
Boundary-scan data
TDO
t
JTKLDX
t
JTKLOX
1
1
—
—
ns
ns
5, 7
5, 7
JTAG external clock to output high impedance
Boundary-scan data
TDO
t
JTKLDZ
t
JTKLOZ
1
1
25
25
ns
ns
5, 6
5, 6
1
All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK
to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load.
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t(
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example,
t
JTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
(V) relative to the t
JTG
clock reference (K) going to the high (H) state or setup time. Also, t
JTDXKH
symbolizes JTAG
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t
JTG
clock reference (K)
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
3
TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4
Non-JTAG signal input timing with respect to t
TCLK
.
5
Non-JTAG signal output timing with respect to t
TCLK
.
6
Guaranteed by design.
7
Guaranteed by design and device characterization.