Freescale Semiconductor Document Number:MPC8306EC Rev. 2, 09/2011 Technical Data MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications This document provides an overview of the MPC8306 PowerQUICC II Pro processor features.
Overview 1 Overview The MPC8306 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8306 also includes two DMA engines and a 16-bit DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8306.
Overview In summary, the MPC8306 provides users with a highly integrated, fully programmable communications processor. This helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements. 1.
Overview • • • – Asynchronous HDLC (bit rate up to 2 Mbps) – Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference Manual with Protocol Interworking.
Overview • • • • — Programmable highest priority request — Six groups of interrupts with programmable priority — External and internal interrupts directed to host processor — Unique vector number for each interrupt source Enhanced secure digital host controller (eSDHC) — Compatible with the SD Host Controller Standard Specification Version 2.0 with test event register support — Compatible with the MMC System Specification Version 4.2 — Compatible with the SD Memory Card Specification Version 2.
Overview • • • • • • • • DMA Engine — Support for the DMA engine with the following features: – Sixteen DMA channels – All data movement via dual-address transfers: read from source, write to destination – Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations – Channel activation via one of two methods (for both the methods, one activation per execution of the minor loop is required): – Explicit software initiation – Initiation via a channel-to-channel linking m
Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8306. The MPC8306 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.
Electrical Characteristics 2.1.2 Power Supply Voltage Specification The following table provides the recommended operating conditions for the MPC8306. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Symbol Recommended Value Unit Note Core supply voltage VDD 1.0 V ± 50 mV V 1 PLL supply voltage AVDD1 AVDD2 AVDD3 1.0 V ± 50 mV V 1 GVDD 1.
Electrical Characteristics 2.1.3 Output Driver Characteristics The following table provides information on the characteristics of the output driver strengths. Table 3. Output Drive Capability Output Impedance () Supply Voltage (V) Local bus interface utilities signals 42 OVDD = 3.3 DDR2 signal 18 GVDD = 1.8 DUART, system control, I2C, SPI, JTAG 42 OVDD = 3.3 GPIO signals 42 OVDD = 3.3 Driver Type 2.1.
Power Characteristics I/O Voltage (GVDD and OVDD) V Core Voltage (VDD) 0.7 V 90% t 0 PORESET >= 32 tSYS_CLK_IN Figure 3. MPC8306 Power-Up Sequencing Example 3 Power Characteristics The typical power dissipation for this family of MPC8306 devices is shown in the following table. Table 5. MPC8306 Power Dissipation Core Frequency (MHz) QUICC Engine Frequency (MHz) CSB Frequency (MHz) Typical Maximum Unit Note 133 133 133 0.272 0.618 W 1, 2, 3 200 233 133 0.291 0.
Clock Input Timing The following table shows the estimated typical I/O power dissipation for the device. Table 6. Typical I/O Power Dissipation Interface Parameter DDR I/O 65% utilization 1.8 V Rs = 20 Rt = 50 1 pair of clocks 266 MHz, 1 16 bits Local bus I/O load = 25 pF 1 pair of clocks 66 MHz, 26 bits QUICC Engine block and other I/Os TDM serial, HDLC/TRAN serial, DUART, MII, RMII, Ethernet management, USB, SPI, Timer output, FlexCAN, eSDHC GVDD (1.8 V) OVDD (3.3 V) Unit Comments 0.
RESET Initialization 4.2 AC Electrical Characteristics The primary clock source for the MPC8306 is SYS_CLK_IN. The following table provides the clock input (SYS_CLK_IN) AC timing specifications for the MPC8306. These specifications are also applicable for QE_CLK_IN. Table 8. SYS_CLK_IN AC Timing Specifications Parameter/Condition Symbol Min Typical Max Unit Note SYS_CLK_IN frequency fSYS_CLK_IN 24 — 66.67 MHz 1 SYS_CLK_IN cycle time tSYS_CLK_IN 15 — 41.6 ns — tKH, tKL 1.1 — 2.
DDR2 SDRAM The following table provides the PLL lock times. Table 10. PLL Lock Times Parameter/Condition Min Max Unit Note — 100 s — PLL lock times 5.1 Reset Signals DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 reset signals mentioned in Table 9. Table 11. Reset Signals DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Note Output high voltage VOH IOH = –6.0 mA 2.
DDR2 SDRAM Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued) Parameter/Condition Symbol Min Max Unit Note Output high current (VOUT = 1.35 V) IOH –13.4 — mA — Output low current (VOUT = 0.280 V) IOL 13.4 — mA — Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to be equal to 0.5 GVDD, and to track GVDD DC variations as measured at the receiver.
DDR2 SDRAM Table 15. DDR2 SDRAM Input AC Timing Specifications (continued) At recommended operating conditions with GVDD of 1.8V ± 100mV. Parameter Symbol 266 MHz Min Max –750 750 Unit Note Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.
DDR2 SDRAM Table 16. DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with GVDD of 1.8V ± 100mV. Symbol1 Parameter MCS output hold with respect to MCK Min Max 2.5 — –0.6 0.6 tDDKHCX 266 MHz MCK to MDQS Skew tDDKHMH MDQ/MDM output setup with respect to MDQS tDDKHDS, tDDKLDS 266 MHz MDQ/MDM output hold with respect to MDQS 0.9 Note ns 3 ns 4 ns 5 ps 5 — tDDKHDX, tDDKLDX 266 MHz Unit 1100 — MDQS preamble start tDDKHMP 0.
DDR2 SDRAM The following figure shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK MCK tMCK tDDKHMH(max) = 0.6 ns MDQS tDDKHMH(min) = –0.6 ns MDQS Figure 5. Timing Diagram for tDDKHMH The following figure shows the DDR2 SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 NOOP tDDKHMP tDDKHMH MDQS[n] tDDKHME tDDKHDS tDDKLDS MDQ[x]/ MECC[x] D0 D1 tDDKLDX tDDKHDX Figure 6.
Local Bus 7 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8306. 7.1 Local Bus DC Electrical Characteristics The following table provides the DC electrical characteristics for the local bus interface. Table 17. Local Bus DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2 OVDD + 0.3 V Low-level input voltage VIL –0.3 0.8 V High-level output voltage, IOH = –100 A VOH OVDD – 0.
Local Bus The following figure provides the AC test load for the local bus. Z0 = 50 Output RL = 50 OVDD/2 Figure 7. Local Bus AC Test Load The following figures show the local bus signals. These figures has been given indicate timing parameters only and do not reflect actual functional operation of interface.
Local Bus LCLK T1 T3 tLBKHOV tLBKHOZ GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH tLBIXKH UPM Mode Input Signal: LUPWAIT tLBIXKH tLBIVKH Input Signals: LAD[0:15]/LDP[0:3] tLBKHOV tLBKHOZ UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 9. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev.
Ethernet and MII Management LCLK T1 T2 T3 T4 tLBKHOZ tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH tLBIXKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH Input Signals: LAD[0:15] tLBKHOV tLBKHOZ UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 10. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 8 Ethernet and MII Management This section provides the AC and DC electrical characteristics for Ethernet interfaces. 8.
Ethernet and MII Management Table 19. MII and RMII DC Electrical Characteristics Parameter Symbol Conditions Min Max Unit Supply voltage 3.3 V OVDD — 3 3.6 V Output high voltage VOH IOH = –4.0 mA OVDD = Min 2.40 OVDD + 0.3 V Output low voltage VOL IOL = 4.0 mA OVDD = Min GND 0.50 V Input high voltage VIH — — 2.0 OVDD + 0.3 V Input low voltage VIL — — –0.3 0.90 V Input current IIN 0 V VIN OVDD — ±5 A 8.
Ethernet and MII Management The following figure provides the AC test load. Z0 = 50 Output RL = 50 OVDD/2 Figure 11. AC Test Load The following figure shows the MII transmit AC timing diagram. tMTXR tMTX TX_CLK tMTXH tMTXF TXD[3:0] TX_EN TX_ER tMTKHDX Figure 12. MII Transmit AC Timing Diagram 8.2.1.2 MII Receive AC Timing Specifications The following table provides the MII receive AC timing specifications. Table 21.
Ethernet and MII Management The following figure shows the MII receive AC timing diagram. tMRXR tMRX RX_CLK tMRXF tMRXH RXD[3:0] RX_DV RX_ER Valid Data tMRDVKH tMRDXKH Figure 13. MII Receive AC Timing Diagram 8.2.2 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 8.2.2.1 RMII Transmit AC Timing Specifications The following table provides the RMII transmit AC timing specifications. Table 22.
Ethernet and MII Management The following figure shows the RMII transmit AC timing diagram. tRMXR tRMX REF_CLK tRMXH tRMXF TXD[1:0] TX_EN tRMTKHDX Figure 15. RMII Transmit AC Timing Diagram 8.2.2.2 RMII Receive AC Timing Specifications The following table provides the RMII receive AC timing specifications. Table 23. RMII Receive AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Ethernet and MII Management The following figure shows the RMII receive AC timing diagram. tRMXR tRMX REF_CLK tRMXF tRMXH RXD[1:0] CRS_DV RX_ER Valid Data tRMRDVKH tRMRDXKH Figure 16. RMII Receive AC Timing Diagram 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock).
Ethernet and MII Management Table 25. MII Management AC Timing Specifications (continued) At recommended operating conditions with OVDD is 3.3 V ± 300mV. Symbol1 Min Typical Max Unit Note MDC to MDIO delay tMDKHDX 10 — 70 ns — MDIO to MDC setup time tMDDVKH 8.5 — — ns — MDIO to MDC hold time tMDDXKH 0 — — ns — MDC rise time tMDCR — — 10 ns — MDC fall time tMDHF — — 10 ns — Parameter/Condition Note: 1.
Ethernet and MII Management 8.4 IEEE 1588 8.4.1 DC Specifications The IEEE 1588 DC timing specifications are given in the following table. Table 26. IEEE 1588 DC Electrical Characteristics Characteristic Symbol Condition Min Max unit Output high voltage VOH IOH = -8.0 mA 2.4 — V Output low voltage VOL IOL = 8.0 mA — 0.5 V IOL = 3.2mA — 0.4 V Output low voltage VOL Input high voltage VIH — 2.0 OVDD + 0.3 V Input low voltage VIL — - 0.3 0.
TDM/SI The following figure provides the data and command output timing diagram. tT1588CLKOUT tT1588CLKOUTH TSEC_1588_CLK_OUT tT1588OV TSEC_1588_PULSE_OUT TSEC_1588_TRIG_OUT Note: The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is count starting falling edge. Figure 18. IEEE 1588 Output AC Timing The following figure provides the data and command input timing diagram. tT1588CLK tT1588CLKH TSEC_1588_CLK TSEC_1588_TRIG_IN tT1588TRIGH Figure 19.
HDLC 9.2 TDM/SI AC Timing Specifications The following table provides the TDM/SI input and output AC timing specifications. Table 29. TDM/SI AC Timing Specifications1 Symbol2 Min Max Unit TDM/SI outputs—External clock delay tSEKHOV 2 14 ns TDM/SI outputs—External clock High Impedance tSEKHOX 2 10 ns TDM/SI inputs—External clock input setup time tSEIVKH 5 — ns TDM/SI inputs—External clock input hold time tSEIXKH 2 — ns Characteristic Notes: 1.
HDLC 10.1 HDLC DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 HDLC protocol. Table 30. HDLC DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH = –2.0 mA 2.4 — V Output low voltage VOL IOL = 3.2 mA — 0.5 V Input high voltage VIH — 2.0 OVDD + 0.3 V Input low voltage VIL — –0.3 0.8 V Input current IIN 0 V VIN OVDD — ±5 A 10.
USB Figure 23 and Figure 24 represent the AC timing from Table 31. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. The following figure shows the timing with external clock. Serial CLK (Input) tHEIXKH tHEIVKH Input Signals: (See Note) tHEKHOV Output Signals: (See Note) tHEKHOX Note: The clock edge is selectable. Figure 23.
USB Table 32. USB DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2.0 OVDD + 0.3 V Low-level input voltage VIL –0.3 0.8 V Input current IIN — ±5 A High-level output voltage, IOH = –100 A VOH OVDD – 0.2 — V Low-level output voltage, IOL = 100 A VOL — 0.2 V Table 33.
DUART 12 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8306. 12.1 DUART DC Electrical Characteristics The following table provides the DC electrical characteristics for the DUART interface of the MPC8306. Table 34. DUART DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2 OVDD + 0.3 V Low-level input voltage OVDD VIL –0.3 0.8 V High-level output voltage, IOH = –100 A VOH OVDD – 0.
eSDHC 13 eSDHC This section describes the DC and AC electrical specifications for the eSDHC interface of the device. 13.1 eSDHC DC Electrical Characteristics The following table provides the DC electrical characteristics for the eSDHC interface. Table 36. eSDHC Interface DC Electrical Characteristics At recommended operating conditions with OVDD = 3.3 V Characteristic Symbol Condition Min Max Unit Note Input high voltage VIH — 0.625 OVDD — V 1 Input low voltage VIL — — 0.
eSDHC Table 37. eSDHC AC Timing Specifications (continued) At recommended operating conditions with OVDD = 3.3 V Symbol1 Min Max Unit Notes Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIXKH 2.5 — ns 3, 4 Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV –3 3 ns 4 Parameter Notes: 1.
FlexCAN 14 FlexCAN This section describes the DC and AC electrical specifications for the FlexCAN interface. 14.1 FlexCAN DC Electrical Characteristics The following table provides the DC electrical characteristics for the FlexCAN interface. Table 38. FlexCAN DC Electrical Characteristics (3.3V) For recommended operating conditions, see Table 2 Parameter Symbol Min Max Unit Notes Input high voltage VIH 2 — V 1 Input low voltage VIL — 0.
I2 C 15 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8306. 15.1 I2C DC Electrical Characteristics The following table provides the DC electrical characteristics for the I2C interface of the MPC8306. Table 40. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 300mV. Parameter Symbol Min Max Unit Notes Input high voltage level VIH 0.7 OVDD OVDD + 0.3 V — Input low voltage level VIL –0.3 0.
I2 C Table 41. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 40). Symbol1 Min Max Unit tI2CF 20 + 0.1 CB4 300 ns Setup time for STOP condition tI2PVKH 0.6 — s Bus free time between a STOP and START condition tI2KHDX 1.3 — s Noise margin at the LOW level for each connected device (including hysteresis) VNL 0.1 OVDD — V Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.
Timers 16 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8306. 16.1 Timer DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 timer pins, including TIN, TOUT, TGATE, and RTC_PIT_CLK. Table 42. Timer DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH = –6.0 mA 2.4 — V Output low voltage VOL IOL = 6.0 mA — 0.
GPIO 17 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8306. 17.1 GPIO DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 GPIO. Table 44. GPIO DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Notes Output high voltage VOH IOH = –6.0 mA 2.4 — V 1 Output low voltage VOL IOL = 6.0 mA — 0.5 V 1 Output low voltage VOL IOL = 3.2 mA — 0.
IPIC 18 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8306. 18.1 IPIC DC Electrical Characteristics The following table provides the DC electrical characteristics for the external interrupt pins of the MPC8306. Table 46. IPIC DC Electrical Characteristics1,2 Characteristic Symbol Condition Min Max Unit Input high voltage VIH — 2.0 OVDD + 0.3 V Input low voltage VIL — –0.3 0.
SPI Table 48. SPI DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH = –6.0 mA 2.4 — V Output low voltage VOL IOL = 6.0 mA — 0.5 V Output low voltage VOL IOL = 3.2 mA — 0.4 V Input high voltage VIH — 2.0 OVDD + 0.3 V Input low voltage VIL — –0.3 0.8 V Input current IIN 0 V VIN OVDD — ±5 A 19.2 SPI AC Timing Specifications The following table and provide the SPI input and output AC timing specifications.
JTAG The following figure shows the SPI timing in slave mode (external clock). SPICLK (Input) tNEIXKH tNEIVKH Input Signals: SPIMOSI (See Note) tNEKHOV Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 34. SPI AC Timing in Slave Mode (External Clock) Diagram The following figure shows the SPI timing in master mode (internal clock).
JTAG Table 50. JTAG Interface DC Electrical Characteristics (continued) Characteristic Symbol Condition Min Max Unit Input high voltage VIH — 2.0 OVDD + 0.3 V Input low voltage VIL — –0.3 0.8 V Input current IIN 0 V VIN OVDD — ±5 A 20.2 JTAG AC Electrical Characteristics This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8306.
JTAG Table 51. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1 (continued) At recommended operating conditions (see Table 2). Symbol2 Min Max Boundary-scan data TDO tJTKLDX tJTKLOX 2 2 — — JTAG external clock to output high impedance: Boundary-scan data TDO tJTKLDZ tJTKLOZ 2 2 19 9 Parameter Output hold times: Unit Notes ns 5 ns 5, 6 6 Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
JTAG The following figure provides the boundary-scan timing diagram. JTAG External Clock VM VM tJTDVKH tJTDXKH Input Data Valid Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs Output Data Valid tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Figure 39. Boundary-Scan Timing Diagram The following figure provides the test access port timing diagram.
Package and Pin Listings 21 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8306 is available in a thermally enhanced MAPBGA (mold array process-ball grid array); see Section 21.1, “Package Parameters for the MPC8306,” and Section 21.2, “Mechanical Dimensions of the MPC8306 MAPBGA,” for information on the MAPBGA. 21.1 Package Parameters for the MPC8306 The package parameters are as provided in the following list.
Package and Pin Listings Figure 41. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8306 MAPBGA Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev.
Package and Pin Listings 21.3 Pinout Listings Following table shows the pin list of the MPC8306. Table 52.
Package and Pin Listings Table 52.
Package and Pin Listings Table 52.
Package and Pin Listings Table 52.
Package and Pin Listings Table 52.
Package and Pin Listings Table 52.
Package and Pin Listings Table 52.
Package and Pin Listings Table 52.
Clocking 22 Clocking The following figure shows the internal distribution of clocks within the MPC8306. Figure 42. MPC8306 Clock Subsystem e300c3 core MPC8306 core_clk Core PLL to DDR memory controller csb_clk DDR Clock Divider /2 MEMC_MCK MEMC_MCK DDR Memory Device ddr_clk Clock Unit SYS_CLK_IN System PLL lbc_clk /n to local bus LBC Clock Divider LCLK[0:1] Local Bus Memory Device csb_clk to rest of the device qe_clk QE_CLK_IN QE PLL CLK Gen Figure 43.
Clocking 22.1 System Clock Domains As shown in Figure 42, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create four major clock domains: • The coherent system bus clock (csb_clk) • The QUICC Engine clock (qe_clk) • The internal clock for the DDR controller (ddr_clk) • The internal clock for the local bus controller (lbc_clk) The csb_clk frequency is derived from the following equation: csb_clk = SYS_CLK_IN × SPMF Eqn.
Clocking In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. The following table specifies which units have a configurable clock frequency.
Clocking Table 55. System PLL Multiplication Factors RCWL[SPMF] System PLL Multiplication Factor 0000 Reserved 0001 Reserved 0010 ×2 0011 ×3 0100 ×4 0101 ×5 0110 ×6 0111–1111 Reserved coherent system bus clock (csb_clk). The following table shows the expected frequency values for the CSB frequency for selected csb_clk to SYS_CLK_IN ratios. Table 56. CSB Frequency Options SYS_CLK_IN(MHz) SPMF csb_clk : sys_clk_in Ratio 25 33.33 66.67 csb_clk Frequency (MHz) 22.
Clocking Table 57. e300 Core PLL Configuration (continued) RCWL[COREPLL] 0-1 2-5 core_clk : csb_clk Ratio VCO Divider 6 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 10 0001 1 1.5:1 8 11 0001 1 1.5:1 8 00 0010 0 2:1 2 01 0010 0 2:1 4 10 0010 0 2:1 8 11 0010 0 2:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 11 0010 1 2.
Clocking Table 58. QUICC Engine PLL Multiplication Factors (continued) RCWL[CEPMF] RCWL[CEPDF] QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/ (1 + RCWL[CEPDF) 00111 0 7 01000 0 8 01001–11111 0 Reserved The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in the following table. Table 59.
Clocking Table 60. Suggested PLL Configurations CEDF Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz) QUICC Engine Frequency (MHz) Conf No. SPMF Core PLL 1 0100 0000100 0111 0 33.33 133.33 266.66 233 2 0010 0000100 0111 1 66.67 133.33 266.66 233 3 0100 0000101 0111 0 33.33 133.33 333.33 233 4 0101 0000101 1001 0 25 125 312.5 225 5 0010 0000101 0111 1 66.67 133.33 333.
Thermal 23 Thermal This section describes the thermal specifications of the MPC8306. 23.1 Thermal Characteristics The following table provides the package thermal characteristics for the 369, 19 19 mm MAPBGA of the MPC8306. Table 61.
Thermal TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. As a general statement, the value obtained on a single layer board is appropriate for a tightly packed printed-circuit board.
Thermal TT = thermocouple temperature on top of package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package.
System Design Information lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force. If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements. 23.2.
System Design Information 24.2 PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins. The voltage level at each AVDDn pin should always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a low frequency filter scheme such as the following.
System Design Information to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS tantalum or Sanyo OSCON). 24.4 Output Buffer DC Impedance For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 45).
Ordering Information The following table summarizes the signal impedance targets. The driver impedance is targeted at minimum VDD, nominal OVDD, 105C. Table 62. Impedance Characteristics Impedance Local Bus, Ethernet, DUART, Control, Configuration and Power Management DDR DRAM Symbol Unit RN 42 Target 20 Target Z0 Ω RP 42 Target 20 Target Z0 Ω Differential NA NA ZDIFF Ω Note: Nominal supply voltages. See Table 1, Tj = 105C. 24.
Ordering Information Table 63. Part Numbering Nomenclature MPC nnnn C VM AF D C A Product Code Part Identifier Temperature Range1 Package2 e300 Core Frequency3 DDR2 Frequency QUICC Engine Frequency Revision Level MPC 8306 VM = Pb-free AB = 133MHz AC = 200 MHz AD = 266 MHz AF = 333 MHz Blank = 0 to 105C C = –40 to 105C D = 266 MHz F = 333 MHz C = 233 MHz Contact local Freescale sales office Notes: 1. Contact local Freescale office on availability of parts with C temperature range.
Document Revision History 26 Document Revision History The following table provides a revision history for this document. Table 65. Document Revision History Rev. No. Date 2 09/2011 • Added Power numbers for core frequency of 333 MHz in Table 5. • Added new PLL configurations as per new core frequency in Table 60. • Added AF to indicate 333 MHz in Table 63. 1 06/2011 • • • • • • 0 03/2011 Initial Release Substantive Change(s) Updated QE frequency in Table 5.
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