Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor 13
DDR2 SDRAM
The following table provides the PLL lock times.
5.1 Reset Signals DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306 reset signals mentioned in
Table 9.
6DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the
MPC8306. Note that DDR2 SDRAM is GV
DD
(typ) = 1.8 V.
6.1 DDR2 SDRAM DC Electrical Characteristics
The following table provides the recommended operating conditions for the DDR2 SDRAM component(s)
of the MPC8306 when GV
DD
(typ) = 1.8 V.
Table 10. PLL Lock Times
Parameter/Condition Min Max Unit Note
PLL lock times — 100 s—
Table 11. Reset Signals DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit Note
Output high voltage V
OH
I
OH
= –6.0 mA 2.4 — V 1
Output low voltage V
OL
I
OL
= 6.0 mA — 0.5 V 1
Output low voltage V
OL
I
OL
= 3.2 mA — 0.4 V 1
Input high voltage V
IH
—2.0OV
DD
+0.3 V 1
Input low voltage V
IL
—–0.30.8V—
Input current I
IN
0 V  V
IN
 OV
DD
— ±5 A—
Note:
1. This specification applies when operating from 3.3 V supply.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV
DD
(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Note
I/O supply voltage GV
DD
1.7 1.9 V 1
I/O reference voltage MVREF 0.49  GV
DD
0.51  GV
DD
V2
I/O termination voltage V
TT
MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage V
IH
MVREF+ 0.125 GV
DD
+0.3 V —
Input low voltage V
IL
–0.3 MVREF – 0.125 V —
Output leakage current I
OZ
–9.9 9.9 A4