Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
30 Freescale Semiconductor
HDLC
9.2 TDM/SI AC Timing Specifications
The following table provides the TDM/SI input and output AC timing specifications.
The following figure provides the AC test load for the TDM/SI.
Figure 20. TDM/SI AC Test Load
The following figure represents the AC timing from Table 29. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 21. TDM/SI AC Timing (External Clock) Diagram
10 HDLC
This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
of the MPC8306.
Table 29. TDM/SI AC Timing Specifications
1
Characteristic Symbol
2
Min Max Unit
TDM/SI outputs—External clock delay t
SEKHOV
214ns
TDM/SI outputs—External clock High Impedance t
SEKHOX
210ns
TDM/SI inputs—External clock input setup time t
SEIVKH
5—ns
TDM/SI inputs—External clock input hold time t
SEIXKH
2—ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
SEKHOX
symbolizes the TDM/SI
outputs external timing (SE) for the time t
TDM/SI
memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
Output
Z
0
= 50 
OV
DD
/2
R
L
= 50 
TDM/SICLK (Input)
t
SEIXKH
t
SEIVKH
t
SEKHOV
Input Signals:
TDM/SI
(See Note)
Output Signals:
TDM/SI
(See Note)
Note: The clock edge is selectable on TDM/SI.
t
SEKHOX