Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor 31
HDLC
10.1 HDLC DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306 HDLC protocol.
10.2 HDLC AC Timing Specifications
The following table provides the input and output AC timing specifications for HDLC protocol.
The following figure provides the AC test load.
Figure 22. AC Test Load
Table 30. HDLC DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit
Output high voltage V
OH
I
OH
= –2.0 mA 2.4 — V
Output low voltage V
OL
I
OL
= 3.2 mA — 0.5 V
Input high voltage V
IH
—2.0OV
DD
+0.3 V
Input low voltage V
IL
—–0.30.8V
Input current I
IN
0 V  V
IN
OV
DD
— ±5 A
Table 31. HDLC AC Timing Specifications
1
Characteristic Symbol
2
Min Max Unit
Outputs—Internal clock delay t
HIKHOV
09ns
Outputs—External clock delay t
HEKHOV
1 12 ns
Outputs—Internal clock high impedance t
HIKHOX
05.5ns
Outputs—External clock high impedance t
HEKHOX
18ns
Inputs—Internal clock input setup time t
HIIVKH
9—ns
Inputs—External clock input setup time t
HEIVKH
4—ns
Inputs—Internal clock input hold time t
HIIXKH
0—ns
Inputs—External clock input hold time t
HEIXKH
1—ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
HIKHOX
symbolizes the outputs
internal timing (HI) for the time t
serial
memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Output
Z
0
= 50 
OV
DD
/2
R
L
= 50 